Patents by Inventor Yen Chen

Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128151
    Abstract: A package structure includes a bonding substrate, an integrated circuit, and a heat sink metal. The integrated circuit includes an active region facing the bonding substrate. The heat sink metal is located between the bonding substrate and the active region of the integrated circuit. The heat sink metal is electrically insulated with the integrated circuit.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Inventors: Chun-Yen PENG, Kuo-Bin HONG, Shih-Chen CHEN, Hao-Chung KUO
  • Publication number: 20240126003
    Abstract: A light source module and a display device are provided. The light source module includes a light source, a light guide plate, and an optical film set including multiple first optical microstructures having a first surface, multiple second optical microstructures having a second surface, and multiple third optical microstructures having a third surface. Each of the multiple first optical microstructures has a first vertex angle, each of the multiple second optical microstructures has a second vertex angle, and each of the multiple third optical microstructures has a third vertex angle. The third vertex angle is less than the first vertex angle, and the first vertex angle is less than or equal to the second vertex angle. By configuring the aforementioned optical microstructures, the light source module of the disclosure may greatly improve the collimation of light and has favorable luminance.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Applicant: Nano Precision Taiwan Limited
    Inventors: Hsin-Wei Chen, Wen-Yen Chiu, Chao-Hung Weng, Ming-Dah Liu
  • Publication number: 20240125849
    Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 18, 2024
    Inventors: Jung-Yin CHIEN, Po-Yen TSENG, Pin-Lin HUANG, Wen-Chih CHEN
  • Publication number: 20240115790
    Abstract: Disclosed is a drainage bottle system comprising: a system housing, a drainage bottle, a drainage tube, a motorless suction device and a liquid detection device, wherein a piezoelectric suction pump of the motorless suction device generates a negative pressure by means of piezoelectric effect to drive the drainage tube to suck and collect a liquid to be detected into the drainage bottle.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Applicant: PACIFIC HOSPITAL SUPPLY CO., LTD.
    Inventors: Jung-Yen TSAI, Ming-Chung CHEN, Hsuan-Chiao HO
  • Publication number: 20240120282
    Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.
    Type: Application
    Filed: February 20, 2023
    Publication date: April 11, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, SHANG-PIN CHEN, WEI-CHIH CHEN, CHE-YEN HUANG
  • Patent number: 11953910
    Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot encountering an unexpected obstacle traversing an area in which the robot is performing an area coverage task. The sensory data are gathered from an operational camera and one or more auxiliary sensors.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: April 9, 2024
    Assignee: Trifo, Inc.
    Inventors: Zhe Zhang, Weikai Li, Qingyu Chen, Yen-Cheng Liu
  • Patent number: 11956462
    Abstract: Video processing methods and apparatuses for coding a current block comprise receiving input data of a current block, partitioning the current block into multiple sub-blocks, deriving sub-block MVs for the current block according to a sub-block motion compensation coding tool, constraining the sub-block MVs to form constrained sub-block MVs, and encoding or decoding the current block using the constrained sub-block MVs, and applying motion compensation to the current block using the constrained sub-block MVs to encode or decode the current block. The sub-block MVs may be constrained according to a size, width, or height of the current block or a sub-block, an inter prediction direction of one of control point MVs of the current block, the current block, or current sub-block, the control point MVs, or a combination of the above.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Chen-Yen Lai, Chih-Wei Hsu
  • Patent number: 11955553
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20240111138
    Abstract: A catadioptric optical membrane, which is disposed on a surface of a substrate, includes a reflection membrane and a matting membrane. The reflection membrane is disposed on an effective optical path area of the substrate and includes a reflection metal membrane and a reflection oxidation membrane. The reflection oxidation membrane includes a first reflection oxidation membrane and a second reflection oxidation membrane. The reflection metal membrane is farther away from the substrate than the first reflection oxidation membrane. The second reflection oxidation membrane is farther away from the substrate than the reflection metal membrane. The matting membrane is disposed on a non-effective optical path area of the substrate. The matting membrane includes a deep-color membrane and a first anti-reflection membrane. The deep-color membrane includes a deep-color metal membrane and a deep-color oxidation membrane. The deep-color membrane is farther away from the substrate than the first anti-reflection membrane.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventors: Wen-Yu TSAI, Shih-Han CHEN, Chun-Yen CHEN, Cheng-Yu TSAI, Chun-Hung TENG
  • Publication number: 20240112924
    Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Hsu-Hsien Chen, Chen-Shien Chen, Ting Hao Kuo, Chi-Yen Lin, Yu-Chih Huang
  • Patent number: 11947208
    Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 2, 2024
    Assignee: HANNSTAR DISPLAY CORPORATION
    Inventors: Jing-Xuan Chen, Cheng-Yen Yeh, Mu-Kai Kang, Sz-Kai Huang, Ming-Chang Yu
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11948834
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20240104831
    Abstract: One embodiment of a method for generating representations of scenes includes assigning each image included in a set of images of a scene to one or more clusters of images based on a camera pose associated with the image, and performing one or more operations to generate, for each cluster included in the one or more clusters, a corresponding three-dimensional (3D) representation of the scene based on one or more images assigned to the cluster.
    Type: Application
    Filed: June 6, 2023
    Publication date: March 28, 2024
    Inventors: Yen-Chen LIN, Valts BLUKIS, Dieter FOX, Alexander KELLER, Thomas MUELLER-HOEHNE, Jonathan TREMBLAY
  • Publication number: 20240105098
    Abstract: A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 28, 2024
    Applicant: HannStar Display Corporation
    Inventors: Jing-Xuan Chen, Yen-Chung Chen, Mu-Kai Kang, Qi-En Luo, Cheng-Yen Yeh
  • Publication number: 20240105664
    Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 11937574
    Abstract: An interactive device for animals is provided that includes a main body, a driving module and a first rotating member. The main body includes an accommodating groove, an opening, and a communicating channel. The driving module is disposed on the main body. The first rotating member is rotatably disposed in the main body and separates the communicating channel and the accommodating groove. When the driving module drives the first rotating member to rotate in a first rotating direction, the first rotating member drives at least one object disposed in the accommodating groove to enter the communicating channel and leave the main body through the opening.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TOMOFUN CO., LTD.
    Inventors: Chia-Yen Chang, Min-Wei Chen, Yo-Chen Victor Chang
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11942519
    Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 26, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan