Abstract: A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

Abstract: A single-chip tunable bandpass filter is provided having a bandpass filter circuit with all tuning components for the bandpass filter circuit formed on the single-chip to provide a programmed center frequency for the tunable bandpass filter. The bandpass filter circuit may include, but is not limited to, a plurality of serially coupled singe stage biquad filter circuits coupled to an input formed on the single-chip and configured to provide a bandpass filtered output signal to an output formed on the single-chip. The bandpass filtered output may be provided by an output buffer formed on the single-chip. The single-chip includes at least one tuning input to receive data for tuning stored in a data register formed on the single-chip. The data register provides control bits to the tuning components that include a programmable resistor responsive to the control bits to vary the programmable resistor to adjust programmed center frequency.

Abstract: An I/Q imbalance calibration method includes sequentially inputting a first in-phase and quadrature signals calibration signal to a front-end circuit of the transmitter system to acquire and estimate a first and second calibration signal strengths sequentially, wherein a delta estimation is adopted; calculating an I/Q gain imbalance according to estimated first and second calibration signal strengths; sequentially inputting a second in-phase calibration signal and both of the second in-phase and quadrature calibration signal to the front-end circuit of the transmitter system to acquire and estimate a third and fourth calibration signal strengths sequentially, wherein an I/Q gain imbalance compensation is formed on the first in-phase and quadrature calibration signals to generate the second in-phase and quadrature calibration signals; and calculating an I/Q phase imbalance according to estimated third and fourth calibration signal strengths.

Abstract: A multi-band antenna package structure includes a first redistribution layer; an integrated circuit layer, formed on the first redistribution layer, comprising at least one metal via, at least one metal pillar, an integrated circuit chip, and a molding layer, wherein the molding layer is used to fill openings formed by the metal via, the metal pillar and the integrated circuit chip which are disposed on the first redistribution layer, the metal via is electrically connected to one of the first metal patterns of the first redistribution layer; a second redistribution layer, formed on the integrated circuit layer; and a first antenna unit layer, comprising a first dielectric layer and third metal patterns formed in openings of the first dielectric layer, wherein at least one of the third metal patterns is electrically connected to one of the second metal patterns, and the third metal patterns form a first antenna unit.

Abstract: An I/Q imbalance calibration method includes sequentially inputting a first in-phase and quadrature signals calibration signal to a front-end circuit of the transmitter system to acquire and estimate a first and second calibration signal strengths sequentially, wherein a delta estimation is adopted; calculating an I/Q gain imbalance according to estimated first and second calibration signal strengths; sequentially inputting a second in-phase calibration signal and both of the second in-phase and quadrature calibration signal to the front-end circuit of the transmitter system to acquire and estimate a third and fourth calibration signal strengths sequentially, wherein an I/Q gain imbalance compensation is formed on the first in-phase and quadrature calibration signals to generate the second in-phase and quadrature calibration signals; and calculating an I/Q phase imbalance according to estimated third and fourth calibration signal strengths.

Abstract: A apparatus for dynamically modifying filter characteristics of a delta-sigma modulator in order to receive and transmit radio frequency signals over a wide frequency range. The system is used for wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a cellular radio architecture that employs a combination of a single circulator, programmable band-pass sampling radio frequency (RF) front-end and optimized digital baseband that is capable of supporting all current cellular wireless access protocol frequency bands.

Abstract: A single-chip tunable bandpass filter is provided having a bandpass filter circuit with all tuning components for the bandpass filter circuit formed on the single-chip to provide a programmed center frequency for the tunable bandpass filter. The bandpass filter circuit may include, but is not limited to, a plurality of serially coupled singe stage biquad filter circuits coupled to an input formed on the single-chip and configured to provide a bandpass filtered output signal to an output formed on the single-chip. The bandpass filtered output may be provided by an output buffer formed on the single-chip. The single-chip includes at least one tuning input to receive data for tuning stored in a data register formed on the single-chip. The data register provides control bits to the tuning components that include a programmable resistor responsive to the control bits to vary the programmable resistor to adjust programmed center frequency.

Abstract: A wireless wearable high data throughput (big data) brain machine interface apparatus is presented. An implanted recording and transmitting module collects neural data from a plurality of implanted electrodes and wirelessly transmits this over a short distance to a wearable (not implanted) receiving and forwarding module, which communicates the data over a wired communication to a mobile post processing device. The post processing device can send this neural data to an external display or computer enabled device for viewing and/or manipulation. High data throughput is supported by aggregating multiple groups of electrodes by multiple n-channel recording elements, which are multiplexed and then modulated into high frequency wireless communications to the wearable module. Embodiments include use of multiple radiators (multiple polarizations and/or spatially distributed), with beam alignment adjustment.

Abstract: A wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a system and method incorporate a compact receiver array design to support the demand for increased mobile broadband services using a through-silicon vias to interconnect front-end analog functions in SiGe BiCMOS to backend circuitry in CMOS.

Abstract: A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a receiver module having a plurality of signal channels for different frequency bands, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture also includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths. The architecture also includes a dual self-cancellation circuit providing digital and analog cancellation of the transmit signal in the receiver module.

Abstract: A convolution operation method includes the following steps of: performing convolution operations for data inputted in channels, respectively, so as to output a plurality of convolution results; and alternately summing the convolution results of the channels in order so as to output a sum result. A convolution operation device executing the convolution operation method is also disclosed.

Abstract: A convolution operation method includes the following steps of: decomposing a large convolution operation region to multiple small convolution operation regions; the small convolution operation regions perform convolution operations so as to generate partial results, respectively; and summing the partial results as a convolution operation result of the large convolution operation region. A convolution operation device capable of supporting the convolution operation method is also disclosed.

Abstract: A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

Abstract: A method and apparatus for dynamically modifying filter characteristics of a delta-sigma modulator in order to perform signal equalization of a signal in the delta signal modulator. The system is used for wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a cellular radio architecture that employs a combination of a single circulator, programmable band-pass sampling radio frequency (RF) front-end and optimized digital baseband that is capable of supporting all current cellular wireless access protocol frequency bands.

Abstract: A method and apparatus for dynamically modifying filter characteristics of a Delta-Sigma modulator to accommodate for Doppler shift. A transceiver in a wireless cellular communication system for adapt to changes in the RF carrier frequency for maintaining signal integrity by applying a pilot tone in calibration to determine a frequency shift response for a bandpass filter. During operation, the system is operative to determine a Doppler shift and to shift the bandpass filter in response.

Abstract: A method and apparatus for dynamically modifying filter characteristics of a Delta-Sigma modulator to accommodate for Doppler shift. A transceiver in a wireless cellular communication system for adapt to changes in the RF carrier frequency for maintaining signal integrity by applying a pilot tone in calibration to determine a frequency shift response for a bandpass filter. During operation, the system is operative to determine a Doppler shift and to shift the bandpass filter in response.

Abstract: A method and apparatus for dynamically modifying filter characteristics of a Delta-Sigma modulator. The system is used for wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a cellular radio architecture that employs a combination of a single circulator, programmable band-pass sampling radio frequency (RF) front-end and optimized digital baseband that is capable of supporting all current cellular wireless access protocol frequency bands.

Abstract: A wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a radio receiver composed of a demodulator operative to work in a delta sigma mode and a Nyquist mode, and wherein a filter and feedback loop may utilized in response to the modulation mode of an RF signal.

Abstract: A cellular radio architecture that includes a multiplexer coupled to an antenna structure and including multiple signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

Abstract: An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.