Abstract: A signal sensing device includes a body and two signal sensing elements disposed in the body. An insulating layer is sandwiched between the two signal sensing elements. Each of the two signal sensing elements incudes a signal transmission section and a signal sensing section in electrical connection with the signal transmission section. The signal transmission sections are planar antennae parallel to each other and each having an antenna shape of meander-line type. The antenna shape of each transmission section has a vertical projection on a plane parallel to each signal transmission section. The vertical projections of the antenna shapes do not overlap completely. When a portion of the body forms a surrounding portion which surrounds a to-be-sensed target, a portion or an entirety of each signal sensing section is located on the surrounding portion.

Abstract: A signal sensing device includes a signal amplifying structure to amplify the strength of the measured signal. The signal sensing device includes a body, a signal sensing element, and a signal amplifying portion. The signal sensing element is disposed in the body and includes a signal transmission section and a signal sensing section in electrical connection with the signal transmission section. The signal amplifying portion includes a plurality of protruding structures protruding outward from the body. Each of the plurality of protruding structures is cylindrical and has a diameter of 250-400 ?m and a height of 40-75 ?m. When a portion of the body forms a surrounding portion surrounding a to-be-sensed target, a portion or an entirety of the signal sensing section is located on the surrounding portion, and the signal amplifying portion is partially or entirely in contact with the to-be-sensed target.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; a gate overlying the substrate; a channel layer separated from the gate by a dielectric and overlying the gate; source/drain regions on the channel layer, the gate extending between the source/drain regions; an insertion layer conforming to an upper surface of the channel layer and comprising a first material; and a passivation layer conforming to an upper surface of the insertion layer and comprising a second material different from the first material; where the passivation layer has a higher density than the insertion layer, such that the passivation layer mitigates the diffusion of environmental materials towards the channel layer, and where the insertion layer mitigates the diffusion of the second material from the passivation layer into the channel layer.

Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

Abstract: A ferroelectric random access memory (FeRAM) cell may include an oxide insertion layer between the electron barrier layer and the metal glue layer of the source/drain regions of the FeRAM cell. The oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent dissociation and/or out-diffusion of the electron barrier layer at high processing temperatures. Thus, the oxide insertion layer may enable the metal glue layer to be formed over the electron barrier layer with low surface roughness, which may enable increased adhesion between the metal glue layer and the source/drain electrodes of the source/drain regions. In this way, the oxide insertion layer may enable low electrical resistance to be achieved for the FeRAM cell and/or may reduce the likelihood of failures in the FeRAM cell, among other examples.

Abstract: A gait evaluating system including a processor is provided. The processor identifies whether a gait type of the user belongs to a normal gait, a non-neuropathic gait or a neuropathic gait based on step feature values of a user and walking limb feature values of the user. In response to that the gait type of the user belongs to the non-neuropathic gait, the processor controls the display panel to display a first auxiliary information, a second auxiliary information, and a third auxiliary information. The first auxiliary information indicates a potential sarcopenia of the user. The second auxiliary information indicates a dietary guideline for muscle building and muscle strengthening. The third auxiliary information shows a motion instruction video for regaining or maintaining muscle strength of the user.

Abstract: A single-material-double-process parametric laser-wavelength converter includes a pump-laser source, a nonlinear optical material, a first optical reflective element, and a second optical reflective element. The pump-laser source is configured to emit a pump-laser pulse light. The nonlinear optical material receives the pump-laser pulse and generates a signal-laser pulse and a partially depleted pump-laser pulse through optical parametric amplification. The first optical reflective element is configured to reflect the signal-laser pulse back to the same nonlinear optical material. The second optical reflective element is configured to reflect the partially depleted pump-laser pulse back to the same nonlinear optical material. With an appropriate adjustment on the reflecting path lengths, the nonlinear optical material is configured to receive the temporally synchronized signal-laser pulse and the partially depleted pump-laser pulse to generate an idler output through difference frequency generation.

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.

Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.

Abstract: A cone laser-gain module including a pump-light source, a laser rod, and a cone structure, is provided. The cone structure, including a large and a small cone aperture connected by cone axis, is configured to accommodate the laser rod parallel to the cone axis and concentrate the pump light toward the laser rod. The pump light enters the cone structure from a large cone aperture. The laser rod is configured to absorb the pump lights to generate a laser light along a laser-emission axis parallel to the laser-rod axis. In particular, the pump lights, some of which diverge and initially miss the laser rod, are reflected and concentrated on the laser rod by an inner surface of the cone structure. A cone laser amplifier and a cone laser oscillator utilizing single or cascaded cone laser-gain modules are also provided.

Abstract: A device structure can be formed by forming a layer stack comprising a continuous bottom electrode material layer, a continuous dielectric layer, and a continuous dielectric metal oxide layer; increasing an oxygen-to-metal ratio in a top surface portion of the continuous dielectric metal oxide layer by incorporating oxygen atoms into the top surface portion of the continuous dielectric metal oxide layer; depositing a continuous semiconductor layer over the continuous dielectric metal oxide layer; and patterning the continuous semiconductor layer and the layer stack to form a patterned layer stack including a bottom electrode, a dielectric layer, a dielectric metal oxide layer, and a semiconductor layer.

Abstract: Embodiments of the present disclosure provide a method including forming a gate electrode over a substrate, forming a ferroelectric layer over the gate electrode, forming a channel layer over the ferroelectric layer, forming a capping layer over the channel layer, wherein the capping layer includes one or more of CeOx, BeOx, InOx, GaOx, AlOx, SnOx, VOx, WOx, TiOx, ZrOx, NbOx, HfOx, SiOx, TaOx, a binary metal oxide based on any combination of the preceding metal oxides, or a ternary metal oxide based on any combination of the preceding metal oxides, annealing, after forming the capping layer, at a temperature less than 350° C., forming a dielectric layer over the capping layer, and forming a source contact and a drain contact in the dielectric layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a semiconductor substrate, a hydrogen sensing stacked layer disposed over the semiconductor substrate, and a protection layer disposed on the hydrogen sensing stacked layer. The hydrogen sensing stacked layer comprises a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer.

Abstract: A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes first spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes a dielectric layer surrounding the epitaxial structure and the first spacers. The semiconductor structure also includes a second spacer on inner sidewalls of the epitaxial structure, wherein the second spacer comprises a first spacer layer and a second spacer layer over the first spacer layer, wherein a void is enclosed by a bottom surface of the epitaxial structure, top surfaces of the first spacer layer and the second spacer layer and a U-shape profile of the second spacer layer.

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.