Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.

Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

Abstract: The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.

Abstract: The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.