Abstract: An electronic device includes a substrate, a sidewall, a plurality of light emitting elements and an optical element. The sidewall is connected to the substrate. The plurality of light emitting elements are disposed on the substrate. The optical element covers at least two of the plurality of light emitting elements, wherein, in a cross-sectional view of the electronic device, a portion of the optical element is disposed between two adjacent ones of the plurality of light emitting elements, and a height of the sidewall is greater than a thickness of the optical element.

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including a first material and a second material. In some embodiments, the first material is a second row transition metal and the second material is a first row transition metal or second row transition metal. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

Abstract: A semiconductor device comprises: a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has: a p-type buried layer; and a junction field effect region in contact with the p-type buried layer in a gate region. The semiconductor device further comprises: a gate oxide layer on the silicon carbide epitaxial layer; a poly silicon layer on the gate oxide layer; an interlayer dielectric layer on the poly silicon layer; a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.

Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

Abstract: A capacitor device is provided. The capacitor device includes a capacitor structure, a conductive line, an interlayer dielectric (ILD) and a first via conductor. The capacitor structure includes a lower electrode and an upper electrode. The conductive line is leveled with the lower electrode and electrically isolated from the lower electrode. The ILD is disposed over the capacitor structure and the conductive line. The first via conductor is adjacent to the capacitor structure and electrically coupled to the conductive line. A method for manufacturing a capacitor die is also provided.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: An attenuated phase-shifting mask (APSM) includes a substrate, a multi-layer structure, a capping layer and an absorber layer. The substrate has a first side and a second side opposite to the first side. The multi-layer structure is disposed over the first side of the substrate. The capping layer is disposed over the multi-layer structure. The absorber layer is disposed over a portion of the capping layer. The absorber layer includes a first material and a second material different from the first material. A thickness of the absorber layer is between approximately 30 nm and approximately 65 nm. A refractive index (n) of the absorber layer is between approximately 0.860 and approximately 0.945. An extinction coefficient (k) of the absorber layer is between approximately 0.070 and approximately 0.015.

Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Abstract: A method of forming a semiconductor structure includes forming a conductive capping layer over a conductive feature, forming a dielectric layer over the conductive capping layer, forming an opening in the dielectric layer to expose a top surface of the conductive capping layer, forming an inhibitor film at the top surface of the conductive capping layer, depositing a barrier layer on sidewalls of the opening, removing the inhibitor film to expose the top surface of the conductive capping layer, depositing a supplementary liner on the barrier layer and the top surface of the conductive capping layer, and depositing a conductive material on the supplementary liner and filling the opening.

Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

Abstract: A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.

Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

Abstract: A transmitter and a method for dynamically setting a current mode of the transmitter are provided. The transmitter includes a digital signal processing (DSP) circuit and a radio frequency (RF) circuit. The DSP circuit is configured to determine a target current mode by selecting one of multiple candidate current modes of the transmitter according to instantaneous transmitting (TX) information, wherein the instantaneous TX information includes at least one of a resource block (RB) information, a modulation and coding scheme (MCS), and an orthogonal frequency-division multiplexing (OFDM) type of an instantaneous TX signal. The RF circuit is configured to output the instantaneous TX signal, wherein at least one supply voltage and at least one bias voltage of a power amplifier (PA) of the RF circuit is controlled according to the target current mode. More particularly, the multiple candidate current modes correspond to different target power consumptions of the transmitter, respectively.

Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A plurality of raw images are captured with a tilt angle from the semiconductor wafer according to graphic data system (GDS) information regarding a layout of a target die, by an inspection apparatus. A first image-based comparison is performed on the plurality of raw images, by a determining circuitry, to obtain a defect image in the plurality of raw images. A second image-based comparison is performed on a reference image and the defect image, so as to classify a defect type of an image difference in the defect image, by the determining circuitry. The number of the plurality of raw images is greater than 2.

Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.

Abstract: A method for performing antenna tuning control of a wireless transceiver device in a wireless communications system and associated apparatus are provided.

Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.