Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Abstract: A method for performing antenna tuning control of a wireless transceiver device in a wireless communications system and associated apparatus are provided.

Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.

Abstract: A method for generating a user scenario of an electronic device includes detecting a real part and an imaginary part of an input impedance of each antenna of the electronic device, using a plurality of sensors of the electronic device to generate a plurality of sensing signals, and entering at least the real part and the imaginary part of the input impedance of each antenna, and the plurality of sensing signals to a machine learning model to output the user scenario.

Abstract: An electronic device includes a substrate, a sidewall, a plurality of light emitting elements and an optical element. The sidewall is connected to the substrate. The plurality of light emitting elements are disposed on the substrate. The optical element covers at least two of the plurality of light emitting elements, wherein, in a cross-sectional view of the electronic device, a portion of the optical element is disposed between two adjacent ones of the plurality of light emitting elements, and a height of the sidewall is greater than a thickness of the optical element.

Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.

Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index no of the air.

Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

Abstract: An electronic device is provided. The electronic device includes a substrate and a plurality of light-emitting assemblies. The substrate includes a first edge, an edge region, and a central region. The edge region is adjacent to the first edge. The central region is adjacent to the edge region and away from the first edge. The light-emitting assemblies are disposed on the substrate, and each of the light-emitting assemblies has a tuning element and a light-emitting element. The light-emitting assemblies further include a first light-emitting assembly and a second light-emitting assembly. The first light-emitting assembly is disposed in the central region and has a first light-emitting pattern. The second light-emitting assembly is disposed in the edge region and has a second light-emitting pattern. At a viewing angle of 60°, the brightness of the first light-emitting pattern is higher than the brightness of the second light-emitting pattern.

Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.

Abstract: According to an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a lower layer pattern including first periodic patterns having a first pitch is formed, and an upper layer pattern including second periodic patterns having a second pitch different from the first pitch is formed. The first periodic patterns at least partially overlaps the second periodic patterns in plan view. A Moiré fringe pattern of the lower layer pattern and the upper layer pattern is obtained by using an electron beam, and an overlay error between the lower layer pattern and the upper layer pattern is obtained from the Moiré fringe pattern.

Abstract: A method for performing DBO measurements utilizing apertures having a single pole includes using a first aperture plate to measure X-axis diffraction of a composite grating. In some embodiments, the first aperture plate has a first pair of radiation-transmitting regions disposed along a first diametrical axis and on opposite sides of an optical axis that is aligned with a center of the first aperture plate. Thereafter, in some embodiments, a second aperture plate, which is complementary to the first aperture plate, is used to measure Y-axis diffraction of the composite grating. By way of example, the second aperture plate has a second pair of radiation-transmitting regions disposed along a second diametrical axis and on opposite sides of the optical axis. In some cases, the second diametrical axis is substantially perpendicular to the first diametrical axis.

Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index no of the air.

Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.

Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A plurality of raw images are captured with a tilt angle from the semiconductor wafer according to graphic data system (GDS) information regarding a layout of a target die, by an inspection apparatus. A first image-based comparison is performed on the plurality of raw images, by a determining circuitry, to obtain a defect image in the plurality of raw images. A second image-based comparison is performed on a reference image and the defect image, so as to classify a defect type of an image difference in the defect image, by the determining circuitry. The number of the plurality of raw images is greater than 2.

Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index n0 of the air.

Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A plurality of raw images of the semiconductor wafer are obtained according to GDS information regarding a layout of a target die, by an inspection apparatus. A first image-based comparison is performed on the raw images, so as to provide a comparison result, by a determining circuitry. The comparison result indicates whether an image difference is present between the images. One of the raw images having the image difference is assigned as a defect image. A second image-based comparison is performed on a reference image and the defect image, so as to classify a defect type of the image difference, by the determining circuitry. The layout of the target die includes a circuit with a duplicate layout formed by a plurality of same cells. The number of the plurality of raw images is greater than 2.