Patents by Inventor Yen-Liang Chen

Yen-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105751
    Abstract: A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.
    Type: Application
    Filed: February 24, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin
  • Publication number: 20240088195
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20240069449
    Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih HSIEH, Yen-Liang CHEN
  • Publication number: 20240071812
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Publication number: 20240056523
    Abstract: A method for generating a user scenario of an electronic device includes detecting a real part and an imaginary part of an input impedance of each antenna of the electronic device, using a plurality of sensors of the electronic device to generate a plurality of sensing signals, and entering at least the real part and the imaginary part of the input impedance of each antenna, and the plurality of sensing signals to a machine learning model to output the user scenario.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 15, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chin-Wei Hsu, Po-Yu Chen, Po-Chung Hsiao, Yen-Liang Chen
  • Publication number: 20240045268
    Abstract: An electronic device includes a substrate, a sidewall, a plurality of light emitting elements and an optical element. The sidewall is connected to the substrate. The plurality of light emitting elements are disposed on the substrate. The optical element covers at least two of the plurality of light emitting elements, wherein, in a cross-sectional view of the electronic device, a portion of the optical element is disposed between two adjacent ones of the plurality of light emitting elements, and a height of the sidewall is greater than a thickness of the optical element.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Inventors: Chin-Lung TING, Ming-Hui CHU, Fang-Ho LIN, Chia-Lun CHEN, Yen-Liang CHEN
  • Patent number: 11841622
    Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Hsieh, Yen-Liang Chen
  • Patent number: 11835820
    Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index no of the air.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: December 5, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Lung Ting, Ming-Hui Chu, Fang-Ho Lin, Chia-Lun Chen, Yen-Liang Chen
  • Publication number: 20230386808
    Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventor: Yen-Liang CHEN
  • Publication number: 20230386807
    Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventor: Yen-Liang CHEN
  • Publication number: 20230369298
    Abstract: An electronic device is provided. The electronic device includes a substrate and a plurality of light-emitting assemblies. The substrate includes a first edge, an edge region, and a central region. The edge region is adjacent to the first edge. The central region is adjacent to the edge region and away from the first edge. The light-emitting assemblies are disposed on the substrate, and each of the light-emitting assemblies has a tuning element and a light-emitting element. The light-emitting assemblies further include a first light-emitting assembly and a second light-emitting assembly. The first light-emitting assembly is disposed in the central region and has a first light-emitting pattern. The second light-emitting assembly is disposed in the edge region and has a second light-emitting pattern. At a viewing angle of 60°, the brightness of the first light-emitting pattern is higher than the brightness of the second light-emitting pattern.
    Type: Application
    Filed: April 11, 2023
    Publication date: November 16, 2023
    Inventors: Yen-Liang CHEN, Chao-Chun HUANG, Ming-Hui CHU, Yu-Hsuan HSIAO
  • Patent number: 11791141
    Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yen-Liang Chen
  • Publication number: 20230244139
    Abstract: According to an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a lower layer pattern including first periodic patterns having a first pitch is formed, and an upper layer pattern including second periodic patterns having a second pitch different from the first pitch is formed. The first periodic patterns at least partially overlaps the second periodic patterns in plan view. A Moiré fringe pattern of the lower layer pattern and the upper layer pattern is obtained by using an electron beam, and an overlay error between the lower layer pattern and the upper layer pattern is obtained from the Moiré fringe pattern.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Inventor: Yen-Liang CHEN
  • Patent number: 11656391
    Abstract: A method for performing DBO measurements utilizing apertures having a single pole includes using a first aperture plate to measure X-axis diffraction of a composite grating. In some embodiments, the first aperture plate has a first pair of radiation-transmitting regions disposed along a first diametrical axis and on opposite sides of an optical axis that is aligned with a center of the first aperture plate. Thereafter, in some embodiments, a second aperture plate, which is complementary to the first aperture plate, is used to measure Y-axis diffraction of the composite grating. By way of example, the second aperture plate has a second pair of radiation-transmitting regions disposed along a second diametrical axis and on opposite sides of the optical axis. In some cases, the second diametrical axis is substantially perpendicular to the first diametrical axis.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Hsieh, Kai Wu, Yen-Liang Chen, Kai-Hsiung Chen, Po-Chung Cheng, Chih-Ming Ke
  • Publication number: 20230014539
    Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index no of the air.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Inventors: Chin-Lung TING, Ming-Hui CHU, Fang-Ho LIN, Chia-Lun CHEN, Yen-Liang CHEN
  • Publication number: 20230006877
    Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.
    Type: Application
    Filed: July 4, 2022
    Publication date: January 5, 2023
    Inventors: Po-Yu Chen, Yen-Liang Chen, Chi-Tsan Chen, Chao-Wei Wang
  • Publication number: 20220384208
    Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Pin CHEN, Chia Sheng TIEN, Wan-Ting CHIU, Chi Long TSAI, Cyuan-Hong SHIH, Yen Liang CHEN
  • Publication number: 20220383473
    Abstract: Methods and systems for diagnosing a semiconductor wafer are provided. A plurality of raw images are captured with a tilt angle from the semiconductor wafer according to graphic data system (GDS) information regarding a layout of a target die, by an inspection apparatus. A first image-based comparison is performed on the plurality of raw images, by a determining circuitry, to obtain a defect image in the plurality of raw images. A second image-based comparison is performed on a reference image and the defect image, so as to classify a defect type of an image difference in the defect image, by the determining circuitry. The number of the plurality of raw images is greater than 2.
    Type: Application
    Filed: July 28, 2022
    Publication date: December 1, 2022
    Inventors: Yen-Liang CHEN, Jun-Xiu LIU
  • Patent number: 11487157
    Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index n0 of the air.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 1, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Lung Ting, Ming-Hui Chu, Fang-Ho Lin, Chia-Lun Chen, Yen-Liang Chen