Patents by Inventor Yen-Liang Lin
Yen-Liang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11973050Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.Type: GrantFiled: June 2, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
-
Publication number: 20240105751Abstract: A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.Type: ApplicationFiled: February 24, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin
-
Patent number: 11942433Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.Type: GrantFiled: January 17, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
-
Publication number: 20240096609Abstract: The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.Type: ApplicationFiled: January 31, 2023Publication date: March 21, 2024Inventors: Yen-Liang LIN, Yu-Kang HUANG, Yu-Chuan TAI
-
Patent number: 11935804Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
-
Publication number: 20240088195Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
-
Publication number: 20240071812Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
-
Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
-
Publication number: 20240063234Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
-
Publication number: 20240021561Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.Type: ApplicationFiled: August 9, 2023Publication date: January 18, 2024Inventors: Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
-
Publication number: 20240021738Abstract: A semiconductor structure including a substrate, a first well region, a second well region, an isolation, a gate structure, and a dielectric layer is provided. The first well region is disposed in the substrate, wherein a dopant of the first well region includes arsenic. The second well region is disposed in the substrate under the first well region, wherein the second well region has a conductivity type different from that of the first doping region. The isolation is disposed in the substrate and surrounds the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate. The gate structure are disposed sequentially over the substrate and overlaps the first well region. A method of forming the semiconductor structure is also provided.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Inventors: ANHAO CHENG, CHING-HUNG KAO, YEN-LIANG LIN, MENG-I KANG, KAI-CHI WU, CHIEN-WEI LEE
-
Patent number: 11855118Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.Type: GrantFiled: December 15, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
-
Patent number: 11843007Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.Type: GrantFiled: November 17, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
-
Publication number: 20230387172Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
-
Publication number: 20230378205Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
-
Publication number: 20230378116Abstract: Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin
-
Patent number: 11817472Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.Type: GrantFiled: October 18, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
-
Publication number: 20230343642Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.Type: ApplicationFiled: July 1, 2022Publication date: October 26, 2023Inventors: Chia-Wen Zhong, Yen-Liang Lin, Yao-Wen Chang
-
Publication number: 20230335536Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
-
Patent number: 11791299Abstract: Exemplary embodiments for redistribution layers of integrated circuits are disclosed. The redistribution layers of integrated circuits of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.Type: GrantFiled: April 27, 2018Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin