Patents by Inventor Yen-Ming Chen

Yen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098564
    Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 1, 2021
    Inventors: Jin-Mu YIN, Hung-Chao KAO, Hsiang-Ku SHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20210098399
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
    Type: Application
    Filed: July 23, 2020
    Publication date: April 1, 2021
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Chih-Sheng Li, Chih-Hung Lu, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20210091029
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20210091736
    Abstract: An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Inventors: Yen-Chung CHEN, Tsai-Ming YANG, Ting-Hsu CHIEN
  • Publication number: 20210082919
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Publication number: 20210071863
    Abstract: A burner of a gas stove includes a burner body, a partition member, and at least one flame cover. The burner body includes an inlet portion and a base. The inlet portion has at least one inlet passage for injecting gas and air, and the base has at least one mixture passage for mixing the gas and the air. The at least one mixture passage communicates with the at least one inlet passage. The partition member has a plurality of through holes and covers the at least one mixture passage. The at least one flame cover has a plurality of flame holes and covers the partition member. Whereby, the size of the burner of the gas stove could be reduced significantly, and the gas could mix with the air effectively and uniformly.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 11, 2021
    Applicant: GRAND MATE CO., LTD.
    Inventors: CHUNG-CHIN HUANG, CHIN-YING HUANG, HSIN-MING HUANG, HSING-HSIUNG HUANG, YEN-JEN YEH, WEI-LONG CHEN, KUAN-CHOU LIN, TANG-YUAN LUO
  • Publication number: 20210066487
    Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 4, 2021
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20210050460
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
  • Patent number: 10921070
    Abstract: The present disclosure describes a connector assembly for a liquid manifold within a server rack. The connector assembly includes a pipe configured to connect to the liquid manifold. The pipe has a flexible portion configured to accommodate at least one of lateral or vertical manipulation of the pipe while the pipe remains connected to the liquid manifold. The connector assembly further includes a first connector and a second connector configured to form a liquid-tight connection when coupled together. One of the first connector and the second connector is connected to a distal end of the pipe. The other of the first connector and the second connector is configured to connect to a component within the server rack, for supplying coolant from the liquid manifold to the component.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 16, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Hsiang Lee, Chih-Ming Chen, Yen-Yu Liu
  • Patent number: 10923565
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Patent number: 10916475
    Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Ying-Yan Chen, Yen-Ming Chen, Sai-Hooi Yeong, Yung-Sung Yen, Ru-Gun Liu
  • Publication number: 20210036122
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a first metal gate stack disposed over the stack of semiconductor layers, a second metal gate stack interleaved between the stack of semiconductor layers, a source/drain (S/D) feature disposed in the stack of semiconductor layers, and an S/D contact disposed over the S/D feature. In many examples, the S/D feature is separated from a sidewall of the second metal gate stack by a first air gap and the S/D contact is separated from a sidewall of the first metal gate stack by a second air gap.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20210034871
    Abstract: An electronic device configured to display interactive information is provided, including a communication device, a camera, an input device, a processor and a display. The camera acquires an input image including an image of a display device, and the display device displays an interactive image including a default interaction option. The processor generates a virtual option according to the interactive image and superimposes the virtual option on the input image. The default interaction option and the virtual option correspond to a designated device and a designated service, respectively. The display is configured to display the input image and the virtual option. The processor determines whether the default interaction option or the virtual option is enabled when the input device receives an input operation, so as to provide the designated service in the designated device corresponding to the enabled default interaction option or virtual option.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 4, 2021
    Applicant: Wistron Corporation
    Inventors: Chih-Ming Chen, Ming-Hsien Lin, Yen-Chuan Chen
  • Publication number: 20210020517
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
  • Publication number: 20210020757
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Cheng-Yu Yang, Kai-Hsuan Lee, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Patent number: 10896330
    Abstract: An electronic device configured to display interactive information is provided, including a communication device, a camera, an input device, a processor and a display. The camera acquires an input image including an image of a display device, and the display device displays an interactive image including a default interaction option. The processor generates a virtual option according to the interactive image and superimposes the virtual option on the input image. The default interaction option and the virtual option correspond to a designated device and a designated service, respectively. The display is configured to display the input image and the virtual option. The processor determines whether the default interaction option or the virtual option is enabled when the input device receives an input operation, so as to provide the designated service in the designated device corresponding to the enabled default interaction option or virtual option.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: January 19, 2021
    Assignee: Wistron Corporation
    Inventors: Chih-Ming Chen, Ming-Hsien Lin, Yen-Chuan Chen
  • Publication number: 20210014325
    Abstract: A data capturing device and a data calculation system and method are provided. The data capturing device transmits sensing data to a computing device, and receives a machine learning model and a library corresponding to a current scene from the computing device. The data capturing device runs the machine learning model to capture feature data from the sensing data, runs the library to convert a requirement into a service task, and then transmits the feature data and the service task.
    Type: Application
    Filed: August 27, 2019
    Publication date: January 14, 2021
    Applicant: Wistron Corporation
    Inventors: Chih-Ming Chen, Yen-Chuan Chen
  • Publication number: 20210013301
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20200411530
    Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.
    Type: Application
    Filed: April 13, 2020
    Publication date: December 31, 2020
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen