Patents by Inventor Yen-Ming Chen

Yen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SHIELDING STRUCTURES
    Publication number: 20210091029
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Replacement Gate Process for FinFET
    Publication number: 20210082919
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Self-aligned contact air gap formation
    Patent number: 10923565
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Semiconductor device and a method for fabricating the same
    Patent number: 10916475
    Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Ying-Yan Chen, Yen-Ming Chen, Sai-Hooi Yeong, Yung-Sung Yen, Ru-Gun Liu
  • Methods of Reducing Parasitic Capacitance in Multi-Gate Field-Effect Transistors
    Publication number: 20210036122
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a first metal gate stack disposed over the stack of semiconductor layers, a second metal gate stack interleaved between the stack of semiconductor layers, a source/drain (S/D) feature disposed in the stack of semiconductor layers, and an S/D contact disposed over the S/D feature. In many examples, the S/D feature is separated from a sidewall of the second metal gate stack by a first air gap and the S/D contact is separated from a sidewall of the first metal gate stack by a second air gap.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH DUMMY FIN STRUCTURE
    Publication number: 20210020517
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
  • Semiconductor Devices with Reduced Parasitic Capacitance
    Publication number: 20210020757
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Cheng-Yu Yang, Kai-Hsuan Lee, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210013301
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Dielectric Inner Spacers in Multi-Gate Field-Effect Transistors
    Publication number: 20200411667
    Abstract: A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.
    Type: Application
    Filed: April 13, 2020
    Publication date: December 31, 2020
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Hybrid SRAM Design with Nano-Structures
    Publication number: 20200411530
    Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.
    Type: Application
    Filed: April 13, 2020
    Publication date: December 31, 2020
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Method for forming semiconductor device structure with cap layer
    Patent number: 10879395
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin structure, and a second fin structure. The method includes forming a gate structure over the first fin structure and the second fin structure. The method includes forming a first source structure and a first drain structure on the first fin structure and on two opposite sides of the gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The method includes forming a cap layer over the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element, and the cap layer adjacent to a top surface of the first source structure is thicker than the cap layer adjacent to a bottom surface of the first source structure.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Semiconductor Device with Funnel Shape Spacer and Methods of Forming The Same
    Publication number: 20200395465
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Conformal transfer doping method for fin-like field effect transistor
    Patent number: 10868151
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Semiconductor device and method of manufacture
    Patent number: 10868130
    Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Semiconductor device with funnel shape spacer and methods of forming the same
    Patent number: 10867870
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES
    Publication number: 20200388542
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Yen-Ming CHEN
  • Integrated Circuit Device with Source/Drain Barrier
    Publication number: 20200388677
    Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
  • Air gap formation between gate spacer and epitaxy structure
    Patent number: 10861753
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
    Patent number: 10861749
    Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Method of forming FinFET structure with reduced Fin buckling
    Patent number: 10861969
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee