Patents by Inventor Yen-Ping Wang
Yen-Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088070Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
-
Publication number: 20240055371Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.Type: ApplicationFiled: January 9, 2023Publication date: February 15, 2024Inventors: Der-Chyang Yeh, Kuo-Chiang Ting, Yu-Hsiung Wang, Chao-Wen Shih, Sung-Feng Yeh, Ta Hao Sung, Cheng-Wei Huang, Yen-Ping Wang, Chang-Wen Huang, Sheng-Ta Lin, Li-Cheng Hu, Gao-Long Wu
-
Patent number: 11894330Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.Type: GrantFiled: March 22, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai
-
Patent number: 11855011Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.Type: GrantFiled: March 30, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
-
Patent number: 11742219Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.Type: GrantFiled: January 28, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
-
Publication number: 20230091737Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
-
Patent number: 11569562Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.Type: GrantFiled: August 20, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
-
Patent number: 11515173Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.Type: GrantFiled: May 7, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
-
Publication number: 20220359977Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
-
Publication number: 20220336386Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
-
Publication number: 20220320020Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.Type: ApplicationFiled: March 30, 2021Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
-
Publication number: 20220262765Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventors: Ching-Jung Yang, Yen-Ping Wang
-
Publication number: 20220262734Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
-
Patent number: 11417616Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.Type: GrantFiled: July 8, 2020Date of Patent: August 16, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
-
Patent number: 11348874Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.Type: GrantFiled: July 8, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
-
Publication number: 20220157625Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (DO and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
-
Patent number: 11329022Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.Type: GrantFiled: December 28, 2018Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Jung Yang, Yen-Ping Wang
-
Patent number: 11239096Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.Type: GrantFiled: August 11, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
-
Patent number: 11225098Abstract: A system of assessing performance of a photocuring light source includes a photocuring light source unit, a light source control unit, a sensing unit, and a computer unit. The light source unit produces light rays on a work platform of a printing machine. The light source control unit is electrically coupled to and controls the light source unit. The sensing unit is disposed proximally to the light source unit to detect power of the light rays from the light source unit. The computer unit is electrically coupled to the sensing unit and the light source control unit to control the light source unit and record the power of the light rays and operating period of the light source unit. A combination having the system is also disclosed.Type: GrantFiled: March 24, 2020Date of Patent: January 18, 2022Assignee: PRINTING TECHNOLOGY RESEARCH INSTITUTEInventors: Shih-Chang Chang, Chia-Bin Chueh, Kang-Yu Liu, Yen-Ping Wang
-
Publication number: 20220013463Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.Type: ApplicationFiled: July 8, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang