Abstract: A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structure, and an epitaxy structure. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structure is disposed on the semiconductor fins. At least one void is present between the first isolation structure and the epitaxy structure.

Abstract: A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

Abstract: A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

Abstract: A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins. The source/drain structure has a top portion with a W-shape cross section for forming a contact landing region. The semiconductor device may further include a plurality of capping layers located on a plurality of recessed portions of the top portion.

Abstract: A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structure, and an epitaxy structure. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structure is disposed on the semiconductor fins. At least one void is present between the first isolation structure and the epitaxy structure.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

Abstract: A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.

Abstract: A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.

Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.

Abstract: A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.

Abstract: A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.

Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.

Abstract: A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.

Abstract: A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.