Patents by Inventor Yen-Tai Lin
Yen-Tai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130064027Abstract: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Inventors: Meng-Yi Wu, Wein-Town Sun, Yen-Tai Lin, Cheng-Jye Liu, Chiun-Chi Shen
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Patent number: 8373485Abstract: A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.Type: GrantFiled: April 20, 2011Date of Patent: February 12, 2013Assignee: eMemory Technology Inc.Inventors: Chen-Hao Po, Yen-Tai Lin, Way-Chen Wu, Ching-Shan Chien
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Publication number: 20120268188Abstract: A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Applicant: EMEMORY TECHNOLOGY INC.Inventors: Chen-Hao Po, Yen-Tai Lin, Way-Chen Wu, Ching-Shan Chien
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Publication number: 20120032566Abstract: A housing includes a main body having an interface and a plastic portion molded on the interface. The main body defines a nanostructure in the interface. The nanostructure includes a plurality of regular, repeating units. A pitch between the adjacent units is in the range from 10 nanometers to 500 nanometers. A height of each unit is in the range from 10 nanometers to 100 nanometers. A surface roughness of the nanostructure is in the range from 1 nanometer to 10 nanometers.Type: ApplicationFiled: October 28, 2010Publication date: February 9, 2012Applicants: HON HAI PRECISION INDUSTRY CO., LTD., FU TAI HUA INDUSTRY (SHENZHEN) CO., LTD.Inventors: SHYAN-JUH LIU, YEN-TAI LIN, SHA-SHA LIU
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Patent number: 7558119Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.Type: GrantFiled: March 12, 2008Date of Patent: July 7, 2009Assignee: eMemory Technology Inc.Inventor: Yen-Tai Lin
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Patent number: 7453312Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.Type: GrantFiled: May 7, 2008Date of Patent: November 18, 2008Assignee: eMemory Technology Inc.Inventors: Yen-Tai Lin, Ching-Yuan Lin
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Patent number: 7427889Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.Type: GrantFiled: April 28, 2006Date of Patent: September 23, 2008Assignee: eMemory Technology Inc.Inventors: Yen-Tai Lin, Ching-Yuan Lin
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Publication number: 20080218252Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.Type: ApplicationFiled: May 7, 2008Publication date: September 11, 2008Inventors: Yen-Tai Lin, Ching-Yuan Lin
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Patent number: 7405972Abstract: A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged in parallel in column direction and connected with the drain regions of the memory units in one column. The bit lines are arranged in parallel in row direction and connected with the source regions of the memory units in one row. The word lines are arranged in parallel in column direction and connected with the select gates of the memory units in one column. The control lines are arranged in parallel in column direction and connected with the control gates of the memory units in one column. The control lines are grouped by two and electrically connected with each other.Type: GrantFiled: January 22, 2007Date of Patent: July 29, 2008Assignee: eMemory Technology Inc.Inventor: Yen-Tai Lin
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Publication number: 20080175049Abstract: A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged in parallel in column direction and connected with the drain regions of the memory units in one column. The bit lines are arranged in parallel in row direction and connected with the source regions of the memory units in one row. The word lines are arranged in parallel in column direction and connected with the select gates of the memory units in one column. The control lines are arranged in parallel in column direction and connected with the control gates of the memory units in one column. The control lines are grouped by two and electrically connected with each other.Type: ApplicationFiled: January 22, 2007Publication date: July 24, 2008Applicant: EMEMORY TECHNOLOGY INC.Inventor: Yen-Tai Lin
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Publication number: 20080165587Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.Type: ApplicationFiled: March 12, 2008Publication date: July 10, 2008Applicant: eMemory Technology Inc.Inventor: Yen-Tai Lin
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Publication number: 20080159008Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.Type: ApplicationFiled: March 10, 2008Publication date: July 3, 2008Applicant: eMEMORY TECHNOLOGY INC.Inventor: Yen-Tai Lin
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Publication number: 20080056013Abstract: A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.Type: ApplicationFiled: November 7, 2007Publication date: March 6, 2008Inventors: Ching-Yuan Lin, Yen-Tai Lin
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Publication number: 20070252640Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Inventors: Yen-Tai Lin, Ching-Yuan Lin
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Publication number: 20070181937Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.Type: ApplicationFiled: February 9, 2006Publication date: August 9, 2007Inventor: Yen-Tai Lin
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Patent number: 7254086Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.Type: GrantFiled: October 19, 2005Date of Patent: August 7, 2007Assignee: eMemory Technology Inc.Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
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Publication number: 20070159883Abstract: A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.Type: ApplicationFiled: September 13, 2006Publication date: July 12, 2007Inventors: Ching-Yuan Lin, Yen-Tai Lin
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Publication number: 20060262626Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.Type: ApplicationFiled: October 19, 2005Publication date: November 23, 2006Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
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Patent number: 6829166Abstract: A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating voltage to determine whether a channel is induced on the surface of a substrate. The channel corresponds to a number of charges stored on the floating gate. A parasitic capacitor exists between the storage unit and the control unit, and a capacitance of the parasitic capacitor increases when the channel has been induced. The method includes applying a first predetermined voltage to the control unit and measuring a voltage variance generated by the parasitic capacitor to analyze data stored by the storage unit.Type: GrantFiled: September 13, 2002Date of Patent: December 7, 2004Assignee: eMemory Technology Inc.Inventors: Yen-Tai Lin, Shih-Jye Shen
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Patent number: 6819620Abstract: A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.Type: GrantFiled: January 23, 2003Date of Patent: November 16, 2004Assignee: eMemory Technology Inc.Inventors: Yen-Tai Lin, Ching-Yuan Lin, Chien-Hung Ho