Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.

Abstract: The present invention includes a nonvolatile memory structure comprising: nonvolatile memory cell area including write/erase pins, address pins and data input/output pins; conductive contact pads arranged at the periphery area of the nonvolatile memory cell area for power input to operate the nonvolatile memory cell, wherein the conductive contact pads are connected to a power selecting from a positive power, a negative power or the combination thereof. The conductive contact pads include a positive power pin or a negative power pin for providing the operating power.

Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating voltage to determine whether a channel is induced on the surface of a substrate. The channel corresponds to a number of charges stored on the floating gate. A parasitic capacitor exists between the storage unit and the control unit, and a capacitance of the parasitic capacitor increases when the channel has been induced. The method includes applying a first predetermined voltage to the control unit and measuring a voltage variance generated by the parasitic capacitor to analyze data stored by the storage unit.

Abstract: An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

Abstract: A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.

Abstract: A word line driver includes an address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the address decoder. A method of driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.

Abstract: A level shift circuit for shifting an input voltage to an output voltage is provided. The level shift circuit includes at least a complementary metal oxide semiconductor (CMOS) transistor formed on a p-substrate. The CMOS transistor has a PMOS transistor and an NMOS transistor. The NMOS transistor includes a gate electrode, a drain electrode having an n-well formed on the p-substrate and a first n-doped region formed inside the n-well, and a source electrode having a second N-doped region formed on the p-substrate.

Abstract: A novel capacitor design and construction method that uses a stacked structure which is sometimes otherwise used for a so-called floating gate transistor. A first electrical contact is electrically coupled with a conductive region formed in the substrate and with a control gate layer. A second electrical contact is electrically coupled with a floating gate layer, forming a plate between the substrate and control gate layers. The footprint of this capacitor is reduced by using both sides of the floating gate layer as capacitive plate. Parasitic capacitance is relatively reduced. One or more dielectric layers can be formed for both capacitors and for floating gate transistors on the substrate in the same process step or steps.

Abstract: A circuit and a method are disclosed for a Schmitt trigger stage which converts transistor-transistor logic (TTL) into metal oxide semiconductor (MOS) logic signal levels using all MOS devices. The circuit reduces the standby current of the n-channel transistor of the input section of the Schmitt trigger stage by adding a MOS diode to the bottom the input section. When higher than normal supply voltages are used, the standby current of the p-channel transistor of the input section can be reduced by adding a MOS diode to the top of the input section. In addition, a small MOS transistor, connected across the output Schmitt trigger inverter, eliminates leakage currents in that inverter.

Abstract: A first mask includes a well mask formed over a first portion of the wafer to define a first conductive type well in the wafer. A first polysilicon mask is formed over the well mask including a plurality of first structures and a plurality of second structures to cover a first polysilicon layer, thereby defining polysilicon gates. A first implanting mask is formed over the first polysilicon mask for forming second conductive type region. A second implanting mask is formed over the first polysilicon mask for forming first conductive type region. A second polysilicon mask is formed between gates of a second conductive type MOS and gates of a first conductive type MOS. A contact hole mask is formed over the second polysilicon mask for forming contact holes. A metal mask is formed over the contact hole mask for forming connection.

Abstract: This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition.

Abstract: A method, a circuit, and a structure are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and introducing a fifth transistor which is shared by two local wordline decoders. The area occupied by the two eliminated transistors is no longer needed because the fifth transistor can be fitted between two existing transistors without an increase in area.

Abstract: A method and a circuit are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and by reducing the number of inputs to the decoder from three to two. The reduction in inputs is made possible by the method of applying to one of the inputs, when low, a voltage signal v.sub.b which is at least one threshold lower than the voltage signal to the other input, when low. This voltage v.sub.b can be derived from the p-substrate bias voltage.

Abstract: Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.

Abstract: A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type.