Abstract: An antenna array device is provided, which includes a ground plate, a substrate, an antenna array, and multiple patch elements. The substrate is disposed on the ground plate. The antenna array is disposed on the substrate. And the multiple patch elements are disposed on the substrate and arranged around the antenna array, and the multiple patch elements are floating (not connected to the ground plate).

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a fixed portion, a movable portion, a driving assembly and a circuit assembly. The fixed portion has a main axis and a polygonal structure surrounding the main axis. The movable portion is configured to connect an optical member, and is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The circuit assembly is electrically connected to the driving assembly.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

Abstract: A sub-assembly of a medicament delivery device is disclosed having a first part containing a first fastener and a second fastener; a second part of the medicament delivery device sub-assembly having a first counter fastener and a second counter fastener; and a space between the first part and the second part; wherein the space is configured to accommodate a medicament container; wherein the medicament delivery device sub-assembly can have a shipping configuration where the distally directed surface of the first part abuts the proximally directed surface of the second part so that the first part and the second part are detachably attached to each other and an assembled configuration where the fastener of the first part abuts the counter fastener of the second part so that the first part and the second part are undetachably attached to each other.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A semiconductor device is described. The semiconductor device includes a blocking layer disposed on a channel of a substrate, a first seed layer disposed on the blocking layer, and a ferroelectric gate layer formed on the first seed layer. The first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), in which O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

Abstract: A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.