Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: An antenna structure is provided, which includes a substrate, an antenna unit and a metal ground. The substrate includes a first surface and a second surface; the antenna unit disposed on the first surface includes a radiation part, a feeding part and a feeding line, where the feeding line includes a first transmission line and a second transmission line that are perpendicular to each other and connected to each other, and the first transmission line is connected to the radiation part via the feeding part; and the metal ground disposed on the second surface has an edge which is perpendicular to projection of the radiation part to the metal ground; and a resonance slot is disposed on the metal ground, and its position corresponds between projection of the second transmission line to the metal ground and the edge.

Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.

Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.

Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.

Abstract: A semiconductor device is provided. The semiconductor device includes one or more dielectric layers over a photodiode in a substrate. The semiconductor device includes a radiation channeling structure extending through the one or more dielectric layers, wherein the radiation channeling structure overlies the photodiode. The semiconductor device includes a lens overlying the radiation channeling structure. The radiation channeling structure includes a body having a refractive index higher than a refractive index of a material at least partially surrounding the body.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: An antenna structure is provided, which includes a substrate, a ground layer, a multi-branch circuit, and multiple antenna elements. The substrate includes a first surface and a second surface. The ground layer is disposed between the first surface and the second surface. The multi-branch circuit is disposed on the first surface, wherein the multi-branch circuit includes a signal feeding terminal and multiple signal output terminals, wherein multiple feeding branches are formed between the signal feeding terminal and the multiple signal output terminals. The multiple antenna elements is disposed on the second surface, wherein the multiple antenna elements are connected to the multiple signal output terminals through respective via holes, and are configured for beamforming, wherein a length difference between path lengths of the feed branches of two adjacent antenna elements in a horizontal direction is configured for controlling a beam angle of the multiple antenna elements.

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

Abstract: A keyswitch assembly includes a switch module, a support mechanism, a blocking mechanism, an enhancing light source, and a backlight source. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator generates a sensing signal. The signal sensor receives the sensing signal to obtain a sensing strength. The support mechanism is disposed on the substrate. The blocking mechanism is disposed on the substrate and has a light-permeable portion. A portion of the blocking mechanism inserts into or escapes from a gap between the signal generator and the signal sensor. The backlight source is disposed on the substrate and located outside the vertical projection of the blocking mechanism on the substrate. The enhancing light source is disposed on the substrate and located within the vertical projection of the blocking mechanism on the substrate and corresponds to the light-permeable portion.

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Abstract: A keyswitch assembly includes a switch module, a support mechanism, and a blocking mechanism. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator provides a sensing signal. The signal sensor receives the sensing signal to obtain a sensing intensity. The support mechanism is disposed on the substrate. A top portion of the support mechanism moves in response to a pressing force. The blocking mechanism includes a pivoting portion rotatably disposed on the substrate, a connecting piece extending from the pivoting portion and movably connected to the support mechanism to be driven by the top portion to swivel relative to the substrate, and a blocking piece extending from the pivoting portion and driven by the connecting piece to be inserted into or escape from the gap between the signal generator and the signal sensor to change the magnitude of the sensing intensity.