Patents by Inventor Yen-Ting Chen
Yen-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250151335Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.Type: ApplicationFiled: March 8, 2024Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shiang HUANG, Cheng-Yi PENG, Yen-Ting CHEN
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Patent number: 12266655Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.Type: GrantFiled: April 4, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 12266576Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.Type: GrantFiled: July 18, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20250095988Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.Type: ApplicationFiled: December 4, 2024Publication date: March 20, 2025Inventors: Ya-Ting Lin, Yen-Ting Chen, Wei-Han Lai
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Publication number: 20250081650Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer over the substrate, a first photodiode and a second photodiode in the first epitaxial layer, and a trench isolation structure between the first photodiode and the second photodiode. The first photodiode includes a first doped region having a first conductivity type. The first photodiode includes a second doped region, overlying the first doped region, having a second conductivity type different than the first conductivity type. The first photodiode includes a third doped region, overlying the first doped region, having the second conductivity type. A first distance between a sidewall of the third doped region and an uppermost surface of the first epitaxial layer is between about a hundredth to about a fifth of a second distance between a sidewall of the trench isolation structure and the uppermost surface of the first epitaxial layer.Type: ApplicationFiled: August 28, 2023Publication date: March 6, 2025Inventors: Wen-Sheng WANG, Yi-Hsuan Fan, Yen-Ting Chen
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Patent number: 12237230Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.Type: GrantFiled: April 23, 2021Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
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Publication number: 20250063781Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.Type: ApplicationFiled: August 18, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shiang HUANG, Yen-Ting CHEN, Wei-Yang LEE
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Patent number: 12191147Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.Type: GrantFiled: July 27, 2021Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Ting Lin, Yen-Ting Chen, Wei-Han Lai
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Patent number: 12191574Abstract: An antenna array device provided, which includes a substrate, multiple antenna elements, a metal ground plate and a first isolation unit group. The multiple antenna elements are disposed on a first surface of the substrate. The multiple antenna elements have a first polarization direction and a second polarization direction opposite to the first polarization direction. The first isolation unit group is disposed between adjacent two of the multiple antenna elements. An arrangement direction of the first isolation unit group is perpendicular to the first polarization direction and the second polarization direction. The first isolation unit group is two isolation units which are adjacent, each of which comprises an outer end and an inner end opposite to the outer end. The inner end is connected to the metal ground plate disposed on a second surface of the substrate via a second via.Type: GrantFiled: October 5, 2021Date of Patent: January 7, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Chieh-Tsao Hwang, Yen-Ting Chen, Siang-Rong Hsu
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Publication number: 20250001121Abstract: A liquid reservoir includes a liquid storage chamber, a nebulizing module, a detection module, a lid, and a bubble blocking structure. The liquid storage chamber has an opening, and a bottom of the liquid storage chamber has a through hole. The nebulizing module is disposed in the through hole. The detection module is disposed within the liquid storage chamber and adjacent to the through hole. The lid is disposed on the liquid storage chamber and covers the opening. The bubble blocking structure is disposed in the liquid storage chamber, and an orthogonal projection of the bubble blocking structure that is projected to the bottom of the liquid storage chamber at least partially overlaps with the through hole.Type: ApplicationFiled: June 28, 2024Publication date: January 2, 2025Inventors: Chieh-Sheng Cheng, CHUN-CHIA JUAN, CHIA-CHIEN CHANG, YEN-TING CHEN
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Publication number: 20250001103Abstract: A portable nebulizer and a shutdown method of the portable nebulizer are provided. The portable nebulizer includes a medicine storage device, a sensing device, a nebulization device, a driving device and a processing device. The medicine storage device is configured to contain predetermined medical fluid. The sensing device is located in the medicine storage device. The nebulization device is configured to nebulize the predetermined medical fluid and simultaneously transmit a sensing signal to the sensing device. The driving device is electrically connected to the nebulization device and transmits a driving signal to the nebulization device. The processing device is electrically connected to the sensing device and the driving device, and collects electrical information of the sensing signal and electrical information of the driving signal to calculate medical fluid volume indication information.Type: ApplicationFiled: June 28, 2024Publication date: January 2, 2025Inventors: YEN-TING CHEN, CHIEN-SHEN TSAI, CHUN-CHIA JUAN
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Publication number: 20240395902Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Patent number: 12155120Abstract: An antenna array device is provided, which includes a ground plate, a substrate, an antenna array, and multiple patch elements. The substrate is disposed on the ground plate. The antenna array is disposed on the substrate. And the multiple patch elements are disposed on the substrate and arranged around the antenna array, and the multiple patch elements are floating (not connected to the ground plate).Type: GrantFiled: March 21, 2022Date of Patent: November 26, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chieh-Tsao Hwang, Yen-Ting Chen, Siang-Rong Hsu
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Patent number: 12142668Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: GrantFiled: January 3, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Publication number: 20240371648Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Chun-Hao KUNG, Hui-Chi HUANG, Kei-Wei CHEN, Yen-Ting Chen
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Patent number: 12136658Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.Type: GrantFiled: July 10, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240363715Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Ting-Yeh Chen, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin
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Publication number: 20240363426Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
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Publication number: 20240347624Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Jin-Mu Yin, Wei-Yang Lee, Chih-Hao Yu, Yen-Ting Chen, Chia-Pin Lin
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Publication number: 20240347616Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.Type: ApplicationFiled: May 13, 2024Publication date: October 17, 2024Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen