Patents by Inventor Yen Ting Chiang

Yen Ting Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170117309
    Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20170062512
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Cheng-Hsien Chou, Hsiao-Hui Tseng, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Min-Ying Tsai
  • Publication number: 20170062496
    Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Chih-Yu Lai, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yen-Ting Chiang, Yeur-Luen Tu
  • Patent number: 9536810
    Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
  • Publication number: 20160365378
    Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
  • Patent number: 8686527
    Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Fann Ting, Yen-Ting Chiang, Ching-Chun Wang
  • Publication number: 20130341746
    Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
    Type: Application
    Filed: July 24, 2012
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-Fann Ting, Yen-Ting Chiang, Ching-Chun Wang
  • Patent number: 7899727
    Abstract: A securities information service system comprises: a service module and a query module. The service module is used to accept a register request from a user and provide a user record. The query module is used to establish a comparison condition according to the user record. The service module is also used to accept a securities message. When the securities message satisfies the comparison condition, the service module will recommend the securities to the user. The securities information service system recommends the securities to users according to the comparison results in order to raise the users' identification and satisfaction with the recommended securities.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: March 1, 2011
    Assignee: TelePaq Technology Inc.
    Inventor: Yen Ting Chiang
  • Publication number: 20090043711
    Abstract: A securities information service system comprises: a service module and a query module. The service module is used to accept a register request from a user and provide a user record. The query module is used to establish a comparison condition according to the user record. The service module is also used to accept a securities message. When the securities message satisfies the comparison condition, the service module will recommend the securities to the user. The securities information service system recommends the securities to users according to the comparison results in order to raise the users' identification and satisfaction with the recommended securities.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 12, 2009
    Inventor: Yen Ting Chiang