Patents by Inventor Yen Ting Chiang

Yen Ting Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9954022
    Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20180026066
    Abstract: In some embodiments, the present disclosure relates to a method of forming a back-side image (BSI) sensor. The method may be performed by forming an image sensing element within a substrate and forming a pixel-level memory node at a position within the substrate that is laterally offset from the image sensing element. A back-side of the substrate is etched to form one or more trenches that are laterally separated from the image sensing element by the substrate and that vertically overlie the pixel-level memory node. A reflective material is formed within the one or more trenches.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 25, 2018
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Kuan-Tsun Chen
  • Publication number: 20170373117
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 28, 2017
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Patent number: 9812483
    Abstract: In some embodiments, the present disclosure relates to a back-side image (BSI) sensor having a global shutter pixel with a reflective material that prevents contamination of a pixel-level memory node. In some embodiments, the BSI image sensor has an image sensing element arranged within a semiconductor substrate and a pixel-level memory node arranged within the semiconductor substrate at a location laterally offset from the image sensing element. A reflective material is also arranged within the semiconductor substrate at a location between the pixel-level memory node and a back-side of the semiconductor substrate. The reflective material has an aperture that overlies the image sensing element. The reflective material allows incident radiation to reach the image sensing element while preventing the incident radiation from reaching the pixel-level memory node, thereby preventing contamination of the pixel-level memory node.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Kuan-Tsun Chen
  • Publication number: 20170301709
    Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 9754993
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Hsiao-Hui Tseng, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Min-Ying Tsai
  • Patent number: 9728570
    Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 9704904
    Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Lai, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yen-Ting Chiang, Yeur-Luen Tu
  • Publication number: 20170133414
    Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.
    Type: Application
    Filed: November 9, 2015
    Publication date: May 11, 2017
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Publication number: 20170117309
    Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20170117315
    Abstract: In some embodiments, the present disclosure relates to a back-side image (BSI) sensor having a global shutter pixel with a reflective material that prevents contamination of a pixel-level memory node. In some embodiments, the BSI image sensor has an image sensing element arranged within a semiconductor substrate and a pixel-level memory node arranged within the semiconductor substrate at a location laterally offset from the image sensing element. A reflective material is also arranged within the semiconductor substrate at a location between the pixel-level memory node and a back-side of the semiconductor substrate. The reflective material has an aperture that overlies the image sensing element. The reflective material allows incident radiation to reach the image sensing element while preventing the incident radiation from reaching the pixel-level memory node, thereby preventing contamination of the pixel-level memory node.
    Type: Application
    Filed: May 9, 2016
    Publication date: April 27, 2017
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Kuan-Tsun Chen
  • Publication number: 20170062496
    Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Chih-Yu Lai, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yen-Ting Chiang, Yeur-Luen Tu
  • Publication number: 20170062512
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Cheng-Hsien Chou, Hsiao-Hui Tseng, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Min-Ying Tsai
  • Patent number: 9536810
    Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
  • Publication number: 20160365378
    Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Hsiao-Hui Tseng, Ming-Tsong Wang, Shyh-Fann Ting, Wei Chuang Wu
  • Patent number: 8686527
    Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Fann Ting, Yen-Ting Chiang, Ching-Chun Wang
  • Publication number: 20130341746
    Abstract: A semiconductor device is provided. The semiconductor device includes metallization layers supported by a substrate, a diode and a partially doped silicon layer disposed over the metallization layers, a buffer layer disposed over the diode and the partially doped silicon layer; and an anti-reflective coating disposed over the buffer layer, the anti-reflective coating formed from a porous silicon.
    Type: Application
    Filed: July 24, 2012
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-Fann Ting, Yen-Ting Chiang, Ching-Chun Wang
  • Patent number: 7899727
    Abstract: A securities information service system comprises: a service module and a query module. The service module is used to accept a register request from a user and provide a user record. The query module is used to establish a comparison condition according to the user record. The service module is also used to accept a securities message. When the securities message satisfies the comparison condition, the service module will recommend the securities to the user. The securities information service system recommends the securities to users according to the comparison results in order to raise the users' identification and satisfaction with the recommended securities.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: March 1, 2011
    Assignee: TelePaq Technology Inc.
    Inventor: Yen Ting Chiang
  • Publication number: 20090043711
    Abstract: A securities information service system comprises: a service module and a query module. The service module is used to accept a register request from a user and provide a user record. The query module is used to establish a comparison condition according to the user record. The service module is also used to accept a securities message. When the securities message satisfies the comparison condition, the service module will recommend the securities to the user. The securities information service system recommends the securities to users according to the comparison results in order to raise the users' identification and satisfaction with the recommended securities.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 12, 2009
    Inventor: Yen Ting Chiang