Patents by Inventor Yen-Wei Chen

Yen-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381608
    Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240379796
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Publication number: 20240379870
    Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Wu-Wei Tsai, Hai-Ching Chen, Po-Ting Lin, Yan-Yi Chen, Yu-Ming Lin, Chung-Te Lin, Tzer-Min Shen, Yen-Tien Tung
  • Publication number: 20240379540
    Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Liang CHENG, Shih Wei BIH, Yen-Yu CHEN
  • Patent number: 12142664
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20240371648
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Chun-Hao KUNG, Hui-Chi HUANG, Kei-Wei CHEN, Yen-Ting Chen
  • Publication number: 20240365564
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chih-Fan Huang, Wen-Chiung Tu, Liang-Wei Wang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20240363791
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Patent number: 12125783
    Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Shih Wei Bih, Yen-Yu Chen
  • Publication number: 20240342229
    Abstract: The present disclosure relates to an anti-fatigue Lactobacillus composition. The anti-fatigue Lactobacillus composition, which includes at least one of Lactobacillus brevis GKEX, Lactobacillus plantarum GKK1 and Lactobacillus johnsonii GKJ2 as an active ingredient, administered to a healthy subject for a continuous period of time, can significantly improve fatigue-related biochemical indices and prolong aerobic exercise time to exhaustion, and thus can be used as an active ingredient for preparation of various compositions for anti-fatigue and/or improving athletic ability.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, You-Shan TSAI, Tzu-Chun LIN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, Zi-He WU, Yen-Po CHEN
  • Publication number: 20240338804
    Abstract: A method for high dynamic range imaging is provided. The method includes the following stages. A first image from a first sensor capable of sensing a first spectrum is received. A second image from a second sensor capable of sensing a second spectrum is received. The second spectrum has a higher wavelength range as compared to the first spectrum. A first image feature from the first image and a second image feature from the second image are retrieved. The first and second images are fused by referencing the first image feature and the second image feature to generate a final image.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 10, 2024
    Inventors: Pin-Wei CHEN, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Yun-I CHOU, Yu-Hua HUANG, Yen-Yang CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN
  • Publication number: 20240310972
    Abstract: A planning method for a displaying device, comprising: read and decode a device description file with a host of a planning system; display a planning interface on a screen via the host; take an object configuration step to configure at least one graphical object to the at least one display page and set an object parameter of the at least one graphical object; generate a corresponding graphical user interface configuration file via the host. When the planning system is connected to the displaying device, the host transmits the graphical user interface configuration file to the displaying device. A microcontroller of the displaying device displays a corresponding graphical user interface on the displaying module based on the graphical user interface configuration file. In this way, the operation time for the user to plan the graphical user interface could be effectively saved.
    Type: Application
    Filed: August 8, 2023
    Publication date: September 19, 2024
    Applicant: WINSTAR DISPLAY CO., LTD.
    Inventors: YU-PIN LIAO, CHIEN-CHOU HSU, CHIA-HSIANG NI, WEN-WEI CHUNG, SSU-TSUNG CHEN, YING-SHUN LIAO, YEN-HUA LIAO
  • Publication number: 20240307007
    Abstract: An alarm system an alarm method for a medical emergency are provided. The alarm method includes: obtaining a physiological signal of a user by a sensor of a portable electronic device; receiving the physiological signal from the portable electronic device, determining whether an abnormal event has occurred according to the physiological signal, and transmitting first feedback information corresponding to the physiological signal to a server in response to the abnormal event by the terminal device; and outputting an alarm message according to the first feedback information by the server.
    Type: Application
    Filed: November 21, 2023
    Publication date: September 19, 2024
    Applicants: Acer Incorporated, Far Eastern Memorial Hospital
    Inventors: Sheng-Wei Chu, Tsung-Hsien Tsai, Ke-Han Pan, Yueh-Yarng Tsai, Pei-Jung Chen, Jun-Hong Chen, Yen-Wen Wu, Jen-Tang Sun
  • Patent number: 12094948
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Patent number: 12094997
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Patent number: 12087590
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Kung, Hui-Chi Huang, Kei-Wei Chen, Yen-Ting Chen
  • Patent number: 12087522
    Abstract: A backlight module is applied to providing light to a plurality of keyswitches of a keyboard. Each keyswitch has a keycap and an elastic member abutting against the keycap. The backlight module includes a membrane circuit board and a light guide plate. The membrane circuit board has a light emitting diode corresponding to the keyswitch. The light emitting diode is located at a side of the elastic member and emits light to the keycap. The light guide plate is disposed on the membrane circuit board. The light guide plate has a slot hole for containing the light emitting diode and has a hole corresponding to the elastic member. An optical microstructure is formed on the light guide plate for guiding light of the light emitting diode to be incident to the keycap. The elastic member passes through the hole to be disposed on the membrane circuit board.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: September 10, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Po-Wei Tsai, Yen-Chang Chen, Sheng-Yun Yang
  • Patent number: 12074206
    Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
  • Publication number: 20240274667
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one or more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Publication number: 20240273675
    Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.
    Type: Application
    Filed: January 2, 2024
    Publication date: August 15, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Hua Huang, Pin-Wei Chen, Keh-Tsong Li, Shao-Yang Wang, Chia-Hui Kuo, Hung-Chih Ko, Yun-I Chou, Yen-Yang Chou, Chien-Ho Yu, Chi-Cheng Ju, Ying-Jui Chen