Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A nail product curing system for curing nail products includes a housing having a nail treatment space configured to receive a hand of a user and to position one or more nails of the user, and one or more LED light sources on the housing for generating light in the nail treatment space for performing a curing process. The nail product curing system also includes a sensing and controlling system that includes touchless sensors on the housing configured to sense placement of the hand in the nail treatment space, and to control various parameters of the curing process using movement of the user's hands. The sensing and controlling system also includes a circuit board on the housing and a radio transmission controller in signal communication with the circuit board configured to control the LED light sources and the curing process using programmed instructions.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

Abstract: The present invention provides a flexible crystalline silicon photovoltaic module and a manufacturing method therefor. The flexible crystalline silicon photovoltaic module comprises a front panel, a rear panel, an encapsulation layer and a solar cell array; the front panel and the rear panel are respectively arranged outside the encapsulation layer, on which an upper surface and a lower surface of the solar cell array are laminated; and ionomer interlayer films are arranged between the encapsulation layer and the solar cell array.

Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A method for image alignment is provided. The method for image alignment includes the following stages. A first image with a first property from a first sensor is received. A second image with a second property from a second sensor is received. The first property is similar to the second property. The first feature correspondence between the first image and the second image is calculated. A third image with a third property from the first sensor and a fourth image with a fourth property from the second image sensor are received. The third property is different from the fourth property. Image alignment is performed on the third image and the fourth image based on the first feature correspondence between the first image and the second image.

Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: An edge assembly used for a plasma etching system is provided. The edge assembly includes: a focus ring peripherally surrounding an edge portion of a mounting platform mounted in the plasma etching system. The focus ring includes: a lower step portion proximate to the edge portion, the lower step portion extending vertically from a bottom surface of the focus ring to a lower step top surface; and an upper step portion distal to the edge portion, the upper step portion extending vertically from the bottom surface of the focus ring to an upper step top surface and extending radially from an upper step inner side to an upper step outer side. The focus ring is characterized by an air gap located in the upper step portion, and the air gap extends peripherally along a circumstance of the focus ring.

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Abstract: A method of forming a semiconductor device includes following steps. A sacrificial layer is formed in an opening of a substrate. A first doped region is formed in the opening over the sacrificial layer. The substrate is flipped. A portion of the substrate is removed to expose the sacrificial layer. The sacrificial layer is replaced with a first contact.

Abstract: The present invention provides a flow control switch including a pipeline structure, a rotating structure, a position-limiting structure and a knob structure. The pipeline structure includes a tubular body and a ball body rotatably disposed in the tubular body. The rotating structure includes a rotatable element connected to the ball body for driving the ball body to rotate. The position-limiting structure is disposed on the tubular body. The knob structure is liftably disposed on the rotating structure for cooperating with the rotatable element. The position-limiting structure has a first and a second position-limiting groove. The knob structure includes a knob body liftably disposed on the rotatable element and a position-limiting element detachably disposed on the knob body. The position-limiting element is optionally disposed in one of the first and the second position-limiting groove, so as to limit a rotation of the rotatable element relative to the position-limiting structure.

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.