Patents by Inventor Yen-Yu Chen

Yen-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374090
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 28, 2022
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 11366497
    Abstract: A multi-body device includes a first machine body, a second machine body, a rotating member, a first magnetic member, a second magnetic member, and a stopper. The second machine body is pivoted to a pivot side of the first machine body. The rotating member is pivoted to the pivot side of the first machine body and located beside the second machine body. The first magnetic member is disposed at the second machine body. The second magnetic member is disposed at a portion of the rotating member corresponding to the first magnetic member. Two corresponding ends of the first magnetic member and the second magnetic member are magnetically repulsive to each other. The stopper is driven by the second machine body and disposed at the pivot side of the first machine body, so as to stretch into or retreat from a rotation path of the rotating member.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 21, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Cheng-Shi Jiang, Hung-Chung Ku, Yen-Chih Kuo, Chih-Ming Chen, Chih-Liang Chiang, Jeng-Hong Chiu, Cheng-Yu Ko, Zhang-Zheng Lin, Wen-Hong Lu, Jie-Wen Yang
  • Patent number: 11363898
    Abstract: Disclosed is aa buckling structure for a bottle cage, which includes a main frame and a buckling structure, wherein the main frame is used for setting a bottle. The buckling structure is connected to the main frame, and the main frame is positioned and arranged on a setting object through the buckling structure. The buckling structure includes a female fastener and a male fastener, wherein the male fastener is connected to the main frame, and the male fastener is located between the main frame and the female fastener. The male fastener is detachably slidably arranged on the female fastener, and the female fastener is arranged on the setting object, so that the main frame is positioned and arranged on the setting object, and the main frame is easily installed and with high positioning reliability.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: June 21, 2022
    Inventor: Yen-Yu Chen
  • Publication number: 20220181324
    Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Publication number: 20220173036
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 11349015
    Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 11341614
    Abstract: An apparatus including an interface and a processor. The interface may be configured to receive video frames generated by a plurality of capture devices. The processor may be configured to perform operations to detect objects in the video frames received from a first of the capture devices, determine depth information corresponding to the objects detected, determine blending lines in response to the depth information, perform video stitching operations on the video frames from the capture devices based on the blending lines and generate panoramic video frames in response to the video stitching operations. The blending lines may correspond to gaps in a field of view of the panoramic video frames. The blending lines may be determined to prevent the objects from being in the gaps in the field of view. The panoramic video frames may be generated to fit a size of a display.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 24, 2022
    Assignee: Ambarella International LP
    Inventors: I-Husan Chen, Hung Ling Lu, Yen-Yu Chen
  • Publication number: 20220154330
    Abstract: A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
  • Patent number: 11322410
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Publication number: 20220100086
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.
    Type: Application
    Filed: February 16, 2021
    Publication date: March 31, 2022
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20220100087
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 31, 2022
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20220102147
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Publication number: 20220097891
    Abstract: A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).
    Type: Application
    Filed: March 30, 2021
    Publication date: March 31, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Yen Yu CHEN, Shin-Kung CHEN, Yuan-Jung LU, Hsing-Fu PENG
  • Publication number: 20220100088
    Abstract: Metal-comprising resist layers (for example, metal oxide resist layers), methods for forming the metal-comprising resist layers, and lithography methods that implement the metal-comprising resist layers are disclosed herein that can improve lithography resolution. An exemplary method includes forming a metal oxide resist layer over a workpiece by performing deposition processes to form metal oxide resist sublayers of the metal oxide resist layer over the workpiece and performing a densification process on at least one of the metal oxide resist sublayers. Each deposition process forms a respective one of the metal oxide resist sublayers. The densification process increases a density of the at least one of the metal oxide resist sublayers. Parameters of the deposition processes and/or parameters of the densification process can be tuned to achieve different density profiles, different density characteristics, and/or different absorption characteristics to optimize patterning of the metal oxide resist layer.
    Type: Application
    Filed: April 15, 2021
    Publication date: March 31, 2022
    Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20220102175
    Abstract: A substrate boat for use in heat treatment of semiconductor wafers includes support rods and fingers for supporting a substrate in a horizontal orientation in process tools, e.g., furnaces. The substrate is supported in the substrate boat by groups of fingers lying in a common horizontal plane. The fingers contact the substrate at support locations on the back side of the substrate. The fingers have a plurality of different shapes and a substrate surface no contact region.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Tung-Huang CHEN, Chi-Hao KUNG, Yen-Yu CHEN
  • Publication number: 20220081759
    Abstract: Semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. In some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. Each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. At least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 17, 2022
    Inventors: Chen-Yu Lee, Yen-Yu Chen
  • Publication number: 20220059375
    Abstract: A semiconductor process system includes a wafer support and a control system. The wafer support includes a plurality of heating elements and a plurality of temperature sensors. The heating elements heat a semiconductor wafer supported by the support system. The temperature sensors generate sensor signals indicative of a temperature. The control system selectively controls the heating elements responsive to the sensor signals.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 24, 2022
    Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN
  • Patent number: 11257755
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 22, 2022
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Publication number: 20220051952
    Abstract: A deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. The deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. To adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. As a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN, Yi-Ming DAI
  • Patent number: D951280
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 10, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ku-Yun Lee, Yen-Yu Chen, Shih-Han Chan