Patents by Inventor Yen-Yu Chen

Yen-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11223838
    Abstract: A video processing apparatus includes a programmable hardware encoder configured to execute an encoding process on a plurality of input video frames. The video processing apparatus further includes a controller coupled with the programmable hardware encoder. The controller is configured to execute a set of instructions to cause the video processing apparatus to: determine first information of the plurality of input video frames, and adjust the encoding process based on the first information.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 11, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Yen-kuang Chen, Lingjie Xu, Minghai Qin, Ping Chen, Xinyang Yu, Qinggang Zhou
  • Publication number: 20220002020
    Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).
    Type: Application
    Filed: October 15, 2020
    Publication date: January 6, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Ching-Chia YANG, Shin-Kung CHEN, Yuan-Jung LU, Yen-Yu CHEN, Hsing-Fu PENG, Pao-Chen LIN
  • Patent number: 11217486
    Abstract: A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Yang, Feng-Cheng Yang, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Publication number: 20210408011
    Abstract: A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second r
    Type: Application
    Filed: April 8, 2021
    Publication date: December 30, 2021
    Inventors: Hidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN
  • Publication number: 20210408410
    Abstract: The invention provides a flexible panel and a method of fabricating the same. The flexible panel includes a flexible substrate, an overcoat layer and a device layer. The overcoat layer is disposed over and directly contacting the flexible substrate. The device layer is disposed over the overcoat layer. In the invention, the flexible substrate can be directly formed on the carrier, such that an additional layer that helps release between the carrier and the flexible substrate may not be needed, and the flexible substrate can be separated from the carrier by the overcoat layer thereon, thereby reducing the production costs and ensure the quality of the flexible panel.
    Type: Application
    Filed: December 4, 2020
    Publication date: December 30, 2021
    Inventors: Yen-Chung Chen, Mei-Ling Chou, Chia-Yu Liu
  • Patent number: 11211419
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Publication number: 20210398589
    Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.
    Type: Application
    Filed: September 28, 2020
    Publication date: December 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin NIEN, Wei-Chang ZHAO, Chih-Yu LIN, Hidehiro FUJIWARA, Yen-Huei CHEN, Ru-Yu WANG
  • Patent number: 11205475
    Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of the SRAM in response to at least a first NOR output signal.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
  • Publication number: 20210391251
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20210388524
    Abstract: The treatment system provides a feature that may reduce cost of the electrochemical plating process by reusing the virgin makeup solution in the spent electrochemical plating bath. The treatment system provides a rotating filter shaft which receives the spent electrochemical plating bath and captures the additives and by-products created by the additives during the electrochemical plating process. To capture the additives and the by-products, the rotating filter shaft includes one or more types of membranes. Materials such as semi-permeable membrane are used to capture the used additives and by-products in the spent electrochemical plating bath. The treatment system may be equipped with an electrochemical sensor to monitor a level of additives in the filtered electrochemical plating bath.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Zong-Kun LIN, Hsuan-Chih CHU, Chien-Hsun PAN, Yen-Yu CHEN, Yi-Ming DAI
  • Publication number: 20210391255
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen -Yu CHEN, Chung-Liang CHENG
  • Publication number: 20210391206
    Abstract: A robot for transferring a wafer is disclosed. A blade of the robot includes a first sensor on an upper surface of the blade and the second sensor on a back surface of the blade. The first sensor is operable to align the blade with a wafer. The second sensor is operable to align the blade with a holder that holds the wafer.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Wen-Hao CHENG, Yen-Yu CHEN
  • Patent number: 11201059
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20210367032
    Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Yu CHEN, Chung-Liang CHENG
  • Patent number: 11177365
    Abstract: A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Yen-Yu Chen
  • Publication number: 20210351143
    Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hao CHENG, Yen-Yu CHEN, Chih-Wei LIN, Yi-Ming DAI
  • Patent number: 11170252
    Abstract: A face recognition method includes capturing a background of an image; after determining that a face exists in the image, determining a face region of interest (ROI) of the face; capturing a foreground of the image with the face; and comparing the face ROI and the foreground of the image to determine whether the face is authentic or not.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 9, 2021
    Assignee: Wistron Corporation
    Inventor: Yen-Yu Chen
  • Patent number: 11164957
    Abstract: A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Yen-Yu Chen
  • Publication number: 20210333227
    Abstract: A sensor and a method of using the sensor are disclosed. The sensor includes a conductive region in electrical communication with two electrodes, the conductive region including a MXene material combined with a mercaptoimidazolyl metal-ligand complex, wherein the MXene has the formula Mn+1Xn and M is a Group 3 transition metal, Group 4 transition metal, Group 5 transition metal, and Group 6 transition metal, X is carbon, nitrogen or a combination thereof, and n has a value of 1 to 3. The sensor can be used to detect volatile compounds that have a double or triple bond.
    Type: Application
    Filed: December 10, 2020
    Publication date: October 28, 2021
    Inventors: Winston Yen-Yu Chen, Lia Antoaneta Stanciu, Alexander Wei, Aiganym Yermembetova
  • Patent number: D936664
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 23, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yen-Yu Chen, Shih-Han Chan