Patents by Inventor Yen-Yu Chen

Yen-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device having work function metal stack and method of forming the same
    Patent number: 11201059
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • SOURCE/DRAIN ISOLATION STRUCTURES FOR LEAKAGE PREVENTION
    Publication number: 20210367032
    Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Yu CHEN, Chung-Liang CHENG
  • Semiconductor device with adhesion layer
    Patent number: 11177365
    Abstract: A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Yen-Yu Chen
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20210351143
    Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hao CHENG, Yen-Yu CHEN, Chih-Wei LIN, Yi-Ming DAI
  • Face recognition method and computer system thereof
    Patent number: 11170252
    Abstract: A face recognition method includes capturing a background of an image; after determining that a face exists in the image, determining a face region of interest (ROI) of the face; capturing a foreground of the image with the face; and comparing the face ROI and the foreground of the image to determine whether the face is authentic or not.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 9, 2021
    Assignee: Wistron Corporation
    Inventor: Yen-Yu Chen
  • Semiconductor device with adhesion layer and method of making
    Patent number: 11164957
    Abstract: A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Yen-Yu Chen
  • SENSOR FOR DETECTING GAS ANALYTE
    Publication number: 20210333227
    Abstract: A sensor and a method of using the sensor are disclosed. The sensor includes a conductive region in electrical communication with two electrodes, the conductive region including a MXene material combined with a mercaptoimidazolyl metal-ligand complex, wherein the MXene has the formula Mn+1Xn and M is a Group 3 transition metal, Group 4 transition metal, Group 5 transition metal, and Group 6 transition metal, X is carbon, nitrogen or a combination thereof, and n has a value of 1 to 3. The sensor can be used to detect volatile compounds that have a double or triple bond.
    Type: Application
    Filed: December 10, 2020
    Publication date: October 28, 2021
    Inventors: Winston Yen-Yu Chen, Lia Antoaneta Stanciu, Alexander Wei, Aiganym Yermembetova
  • Passivated and faceted for fin field effect transistor
    Patent number: 11158743
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Mathematical accelerator for artificial intelligence applications
    Patent number: 11144282
    Abstract: A system includes an accelerator to accelerate the computations of nonlinear math functions. The accelerator includes a set of first evaluators and a set of second evaluators. Each of the first evaluators and the second evaluators is a fixed-function hardware circuit specialized for evaluating a respective nonlinear function. The system further includes a processor which decodes a math instruction in an instruction set, sends to the accelerator a signal identifying a nonlinear function corresponding to the math instruction, and receives an output of the nonlinear function from the accelerator. According to the signal, the accelerator evaluates the nonlinear function using one of the first evaluators. When the signal identifies the nonlinear function as a composite function, the accelerator additionally uses one of second evaluators on an output of the one first evaluator.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 12, 2021
    Assignee: MediaTek Inc.
    Inventors: Yen-Yu Chen, Wei-Jen Chen, Yu Chia Chen
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210305047
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Jia-Lin WEI, Ming-Hui WENG, Chih-Cheng LIU, Yi-Chen KUO, Yen-Yu CHEN, Yahru CHENG, Jr-Hung LI, Ching-Yu CHANG, Tze-Liang LEE, Chi-Ming YANG
  • BARRIER LAYER FOR METAL INSULATOR METAL CAPACITORS
    Publication number: 20210305356
    Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anhao CHENG, Fang-Ting KUO, Yen-Yu CHEN
  • PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERN
    Publication number: 20210305040
    Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Yi-Chen KUO, Chih-Cheng LIU, Ming-Hui WENG, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210302839
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210302833
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: October 15, 2020
    Publication date: September 30, 2021
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Reducing Metal Gate Overhang By Forming A Top-Wide Bottom-Narrow Dummy Gate Electrode
    Publication number: 20210280692
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 9, 2021
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • PVD TARGET DESIGN AND SEMICONDUCTOR DEVICES FORMED USING THE SAME
    Publication number: 20210238731
    Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.
    Type: Application
    Filed: December 8, 2020
    Publication date: August 5, 2021
    Inventors: Chia-Hsi WANG, Yen-Yu CHEN, Yi-Chih CHEN, Shih Wei BIH
  • Novel Structures for Tuning Threshold Voltage
    Publication number: 20210242092
    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.
    Type: Application
    Filed: July 10, 2020
    Publication date: August 5, 2021
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • AUTOMATED MATERIAL HANDLING SYSTEMS
    Publication number: 20210242057
    Abstract: An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.
    Type: Application
    Filed: December 18, 2020
    Publication date: August 5, 2021
    Inventors: Yen Le LEE, Yen-Yu CHEN, Wei Chih CHEN, Tai Hsiang LIAO, Kai-Ping JHAN
  • Apparatus for fabricating a semiconductor device with target sputtering and target sputtering method for fabricating the semiconductor device
    Patent number: 11081341
    Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device with target sputtering, including a chamber for accommodating a consumable target, a target accumulative consumption counter, wherein the target accumulative consumption counter provides a signal correlated to an amount of the consumable target being consumed, and a power supply communicates with the consumable target counter, wherein the power supply provides a power output according to the signal.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih Wei Bih, Yen-Yu Chen, Yi-Ming Dai
  • Display screen or portion thereof with graphical user interface
    Patent number: D936664
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 23, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yen-Yu Chen, Shih-Han Chan