Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A semiconductor manufacturing method is provided. The semiconductor manufacturing method includes the following steps. A first semiconductor element with a bonding film and a first stressing film is formed. The first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. The first stressing film makes the first bonding film to have a first convex surface. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on one side of the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A knob-driven adjusting mechanism has two fastening belts, one adjusting device, two base seats and two shafts. The fastening belt goes through a long groove. The fastening belt is formed with a tooth row on the side of the long groove. The adjusting device has a shell seat and a knob, and each fastening belt respectively goes through the shell seat. The knob is configured on the shell seat in a rotary form to drive the fastening belts. Each base seat is respectively used for the two side parts configured on an object. The base seat has two protruding support parts. Each shaft is respectively configured on each base seat. The two ends of the shaft respectively goes into each support part in the axial direction. Each shaft is respectively connected to each fastening belt, so that each fastening belt can respectively rotate in relation to the base seat.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: There is provided a smoke detector including a first light source, a second light source surface, a light sensor and a processor. The light sensor receives reflected light when the first light source and the second light source emit light, and generates a first detection signal corresponding to light emission of the first light source and a second detection signal corresponding to light emission of the second light source. The processor distinguishes smoke and floating particles according to a similarity between the first detection signal and the second detection signal.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.