Abstract: A multiple singulated die testing structure and methods for forming the same. In some embodiments, the testing structure includes a cold plate located above an alignment stage that includes a plurality of die testing locations, a plurality of sensors, a plurality of heaters, and a plurality of vacuum sub-channels. Each heater may be located below a corresponding sensor. A vacuum channel may connect to the plurality of vacuum sub-channels located between each sensor. The testing structure may further include a multiple singulated die holder that include die grooves. In some embodiments, the multiple singulated die holder includes a high thermal conductivity material layer and a low thermal conductivity material layer.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A package substrate includes a core, a dielectric filling layer, and a die in the dielectric filling layer, including a device region on a first side of the die, and a through silicon via (TSV) extending from the first side of the die, through the device region, and to a second side of the die opposite the first side of the die. A method of making a package substrate includes providing a core, mounting a die at least one of on the core or in the core, wherein the die includes a device region on a first side of the die, and a TSV extending from the first side of the die, through the device region, and to a second side of the die opposite the first side of the die, and forming a dielectric filling layer around the die.

Abstract: A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.

Abstract: A semiconductor package includes a first die, at least one second die and a thermal dissipation structure. The first die has a first bonding layer. The second die has a second bonding layer, wherein the second die is disposed on the first die, and the second bonding layer is bonded to the first bonding layer. The thermal dissipation structure is disposed on a backside surface of the at least one second die, wherein a thermal conductivity of the thermal dissipation structure is in a range of 120 W/(m·K) to 10,000 W/(m·K), a thickness of the thermal dissipation structure is in a range of 5 ?m to 1,500 ?m, and an area of a surface of the thermal dissipation structure facing the backside surface of the at least one second die is in a range of 10 mm2 to 860 mm2.

Abstract: A method of bonding semiconductor chips is described. The method includes the following steps. A semiconductor wafer is provided on a chuck table of a bonding apparatus. A bond head of the bonding apparatus is driven for picking up a first semiconductor chip from a support, wherein the first semiconductor chip has a first warpage amount. The bond head is driven for moving the first semiconductor chip to a position located over a first bonding region of the semiconductor wafer. A deforming process is performed using a deforming mechanism to deform the chuck table and the first bonding region of the semiconductor wafer by a first deform amount, wherein the first deform amount corresponds to the first warpage amount. The first semiconductor chip is bonded to the first bonding region of the semiconductor wafer while maintaining the first deform amount. The deforming mechanism is released from deforming the chuck table.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.

Abstract: A system on integrated circuit structure including first semiconductor dies, a first insulating encapsulant, a first redistribution circuit structure, a first bonding structure, and a second semiconductor die is provided. The first insulating encapsulant encapsulates the first semiconductor dies. The first redistribution circuit structure is disposed on the first semiconductor dies and the first insulating encapsulant. The first bonding structure is disposed on and electrically connected to the first redistribution circuit structure. The first bonding structure includes a first bonding dielectric layer and first bonding conductors embedded in the first bonding dielectric layer.

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A semiconductor package and the method of forming the same are provided. The semiconductor package may include a package substrate and a first package component over the package substrate. The first package component may include a first semiconductor die and a heat dissipation substrate over the first semiconductor die. The heat dissipation substrate may comprise a base portion and a first coating portion on a first surface of the base portion. The first coating portion may be between the first semiconductor die and the base portion. The base portion may comprise a first material with a first thermal conductivity and the first coating portion may comprise a second material different from the first material. The second material may have a second thermal conductivity smaller than the first thermal conductivity.

Abstract: A stacking structure including a first bonding structure, a first die and a second die is provided. The first die is disposed on a first side of the first bonding structure, and the first die includes a second bonding structure. A first encapsulation material wraps around the first die. The second die is disposed on a second side of the first bonding structure opposite to the first side, and the second die includes a third bonding structure and through die vias. A second encapsulation material wraps around the second die. The second bonding structure of the first die is bonded with the first bonding structure, and the third bonding structure of the second die is bonded with the first bonding structure located between the first and second dies and the first and second encapsulation materials.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: A semiconductor package includes a plurality of first semiconductor dies, a plurality of first bonding pads, a bridge layer, a plurality of second bonding pads and a plurality of second semiconductor dies. The first bonding pads are disposed on the first semiconductor dies. The bridge layer is disposed on the first bonding pads, wherein the bridge layer is electrically connected to the first semiconductor dies through the first bonding pads. The second bonding pads are disposed on the bridge layer, wherein the second bonding pads are electrically connected to the first bonding pads through the bridge layer. The second semiconductor dies are disposed on and electrically connected to the second bonding pads, wherein an active surface of the first semiconductor dies is facing an active surface of the second semiconductor dies.

Abstract: A semiconductor structure includes a source/drain feature, a gate structure disposed adjacent to the source/drain feature, a source/drain contact disposed over and electrically connected to the source/drain feature, an interlayer dielectric (ILD) layer over the source/drain feature and adjacent to the source/drain contact and the gate structure, and an air gap surrounding the source/drain contact and separating the source/drain contact from the ILD layer and the gate structure in a top view.

Abstract: A semiconductor package includes a plurality of first semiconductor dies, a first bonding layer, a redistribution layer, a plurality of second semiconductor dies and a plurality of conductive terminals. The first bonding layer is disposed on the first semiconductor dies, and includes a plurality of first bonding pads. The redistribution layer is disposed on and electrically connected to the first bonding pads. The second semiconductor dies are disposed on and electrically connected to the redistribution layer, wherein backside surfaces of the second semiconductor dies are facing active surfaces of the first semiconductor dies. The conductive terminals are disposed on and electrically connected to the second semiconductor dies.

Abstract: A semiconductor device and a method of forming a semiconductor device are provided. The semiconductor device includes a first die, a diamond layer and an encapsulant. The diamond layer is disposed on the first die. The encapsulant is disposed on the first die, wherein the encapsulant encapsulates the diamond layer.

Abstract: Semiconductor structures and fabrication processes are provided. A semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region.

Abstract: A bonding apparatus includes a chuck table, a gantry frame, a bond head and a gas supplying mechanism. The chuck table is configured to support a semiconductor wafer. The gantry frame is disposed over the chuck table. The bond head is movably installed on the gantry frame, wherein the bond head is configured to pick up a semiconductor chip from a support structure, and for moving the semiconductor chip towards the chuck table for bonding to the semiconductor wafer. The gas supplying mechanism is configured to supply a bonding gas to the semiconductor wafer during the bonding of the semiconductor chip.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).