Patents by Inventor Yeon Cheol Heo
Yeon Cheol Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11127640Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: GrantFiled: February 19, 2020Date of Patent: September 21, 2021Inventor: Yeon-Cheol Heo
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Patent number: 10937700Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.Type: GrantFiled: May 1, 2017Date of Patent: March 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mirco Cantoro, Yun-Il Lee, Hyung-Suk Lee, Yeon-Cheol Heo, Byoung-Gi Kim, Chang-Min Yoe, Seung-Chan Yun, Dong-Hun Lee
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Publication number: 20200185279Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Inventor: Yeon-Cheol Heo
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Patent number: 10622258Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: GrantFiled: January 8, 2019Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Yeon-Cheol Heo
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Patent number: 10461187Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.Type: GrantFiled: June 8, 2018Date of Patent: October 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
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Patent number: 10361319Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.Type: GrantFiled: May 16, 2018Date of Patent: July 23, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
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Publication number: 20190139834Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: ApplicationFiled: January 8, 2019Publication date: May 9, 2019Inventor: Yeon-Cheol Heo
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Patent number: 10276564Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.Type: GrantFiled: April 17, 2017Date of Patent: April 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Yeon Cheol Heo, Byoung Gi Kim, Chang Min Yoe, Seung Chan Yun, Dong Hun Lee, Yun Il Lee, Hyung Suk Lee
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Patent number: 10204834Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: GrantFiled: July 20, 2017Date of Patent: February 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Yeon-Cheol Heo
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Publication number: 20180294353Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode.Type: ApplicationFiled: June 8, 2018Publication date: October 11, 2018Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
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Publication number: 20180269333Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.Type: ApplicationFiled: May 16, 2018Publication date: September 20, 2018Inventors: Mirco CANTORO, Yeon-cheol HEO, Maria Toledano LUQUE
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Patent number: 10020396Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.Type: GrantFiled: November 14, 2016Date of Patent: July 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
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Publication number: 20180166344Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: ApplicationFiled: July 20, 2017Publication date: June 14, 2018Inventor: Yeon-Cheol Heo
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Publication number: 20180151561Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.Type: ApplicationFiled: April 17, 2017Publication date: May 31, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Mirco CANTORO, Yeon Cheol HEO, Byoung Gi KIM, Chang Min YOE, Seung Chan YUN, Dong Hun LEE, Yun Il LEE, Hyung Suk LEE
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Patent number: 9978881Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.Type: GrantFiled: May 18, 2017Date of Patent: May 22, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
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Publication number: 20180130713Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.Type: ApplicationFiled: May 1, 2017Publication date: May 10, 2018Inventors: MIRCO CANTORO, YUN-IL LEE, HYUNG-SUK LEE, YEON-CHEOL HEO, BYOUNG-GI KIM, CHANG-MIN YOE, SEUNG-CHAN YUN, DONG-HUN LEE
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Publication number: 20180040740Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.Type: ApplicationFiled: May 18, 2017Publication date: February 8, 2018Inventors: Mirco CANTORO, Yeon-cheol HEO, Maria Toledano LUQUE
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Publication number: 20170345927Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode.Type: ApplicationFiled: November 14, 2016Publication date: November 30, 2017Inventors: Mirco Cantoro, Yeon-cheol HEO, Maria TOLEDANO LUQUE
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Patent number: 9576955Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.Type: GrantFiled: January 11, 2016Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hwan Lee, Tae Yong Kwon, Sang Su Kim, Chang Jae Yang, Jung Han Lee, Hwan Wook Choi, Yeon Cheol Heo, Sang Hyuk Hong
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Publication number: 20160329327Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.Type: ApplicationFiled: January 11, 2016Publication date: November 10, 2016Inventors: Jae Hwan LEE, Tae Yong KWON, Sang Su KIM, Chang Jae YANG, Jung Han LEE, Hwan Wook CHOI, Yeon Cheol HEO, Sang Hyuk HONG