Patents by Inventor Yeon Cheol Heo

Yeon Cheol Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020160564
    Abstract: A method for forming a semiconductor device having a field oxide layer for isolating elements from each other, wherein the semiconductor device contains a field region and an active region, the active region having a junction region and a channel region, includes the steps of: a) providing a semiconductor structure having a trench in the field region; b) forming a first field insulating layer into the trench; c) forming a conductive layer on the first field insulating layer to fill a predetermined portion of the trench; and d) forming a second field insulating layer on the conductive layer to fill the remaining portion of the trench, thereby reducing an influence of an electric field caused by a potential difference between a semiconductor substrate and a junction region.
    Type: Application
    Filed: March 29, 2000
    Publication date: October 31, 2002
    Inventor: Yeon-Cheol Heo
  • Publication number: 20010015465
    Abstract: The present invention discloses a method for forming transistors for semiconductor devices that can prevent degradation of device properties by interrupting a current path from a drain junction region to a source junction region with an insulating channel barrier structure. The method includes the steps of: forming a device isolating film for defining an active region, and simultaneously forming a channel barrier film at the lower portion of a gate electrode formation region; partially etching the upper portion of the channel barrier film to form a recess; filling the recess above the upper portion of the channel barrier film with silicon; patterning a gate oxide film and a gate electrode on the stacked structure of the channel barrier film and silicon; and forming the transistor by forming source/drain junction regions in the exposed semiconductor substrate.
    Type: Application
    Filed: January 2, 2001
    Publication date: August 23, 2001
    Inventors: Jeong Kug Lee, Yeon Cheol Heo
  • Patent number: 6218232
    Abstract: A method for fabricating a DRAM device, comprising the steps of: providing a SOI substrate upon which a first silicon layer, a buried oxide film and a second silicon layer are stacked; forming an isolation film in the second silicon layer; forming first and second trenches in the second silicon layer and the isolation film; forming gate electrodes in both sidewalls of the first and second trenches; forming first and second impurity regions in the upper surface of both sides of the first trenches and third and fourth impurity regions beneath the first and second trenches by injecting impurity ions into the second silicon layer; forming a capacitor to contact the first and the second impurity regions via first and second contact holes in a first intermediate insulating layer, and a first wiring to contact with the fourth impurity region via third contact hole in the first insulating layer; forming a first conductive layer pattern including a second wiring to contact with the first wiring via fourth contact hole
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: April 17, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Yeon Cheol Heo
  • Patent number: 5926733
    Abstract: The present invention provides metal layer patterns of a semiconductor device which reduces the effect of the current induced by the plasma in the etching process and prevents the device characteristics from being deteriorated, by a method for forming a photomask to pattern metal layers of a semiconductor device including the steps of: designing base metal line patterns, the base metal line patterns being required for the proper operation of the semiconductor device; expanding the base metal line patterns outwardly by an expanding distance; designing a dummy metal line patterns by reversing the expanded base metal line patterns; and designing a final metal line patterns of the semiconductor device by combining the base metal line patterns and the dummy metal line patterns.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: July 20, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Yeon Cheol Heo