Patents by Inventor Yeon Choi

Yeon Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11641156
    Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 2, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Chung Yuen Won, Kwang Su Na, Mi Na Kim, Bong Yeon Choi, Kyoung Min Kang, Hoon Lee, Chang Gyun An, Tae Gyu Kim, Jun Sin Yi
  • Patent number: 11637170
    Abstract: A display device, includes: pixels at a display area; gate lines at the display area, and connected to the pixels; carry clock lines and scan clock lines at the display area; and a gate driving circuit distributedly located at the display area, and connected to the carry clock lines, the scan clock lines, and the gate lines. The gate driving circuit includes a plurality of stages, each of the stages to output, as a carry signal, a carry clock signal supplied through a corresponding carry clock line from among the carry clock lines, and to output, as a scan signal, a scan clock signal supplied through a corresponding scan clock line from among the scan clock lines. The corresponding carry clock line and the corresponding scan clock line corresponding to one stage from among the stages are spaced from each other with at least one of the pixels interposed therebetween.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 25, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Yong No, Tae Ho Kang, Kwi Hyun Kim, Hwa Rang Lee, Ji Yeon Choi
  • Publication number: 20230116395
    Abstract: A fingerprint sensor includes a substrate, a sensor pixel disposed on the substrate and including a light sensing element through which a sensing current flows according to an amount of incident light, a light-blocking conductive layer disposed on the sensor pixel and including a plurality of holes, a first fingerprint pad disposed on the substrate, and a conductive connector connected to the first fingerprint pad and to which a predetermined voltage is applied. The light-blocking conductive layer is electrically connected to the conductive connector.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 13, 2023
    Inventors: Jeong Heon LEE, Young Sik KIM, Jung Hak KIM, Kyo Won KU, Hee Yeon CHOI
  • Patent number: 11591923
    Abstract: Disclosed herein are a ring segment having an air pouch and a first cooling hole formed therein, and a turbine including the same. The air pouch and the first cooling hole are formed in a shield wall, thereby achieving an improvement in cooling performance as well as simplification of production process.
    Type: Grant
    Filed: September 25, 2022
    Date of Patent: February 28, 2023
    Assignee: DOOSAN ENERBILITY CO., LTD.
    Inventors: Young Gi Mun, Ha Neul Kim, Jae Yeon Choi
  • Publication number: 20230041072
    Abstract: A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Applicant: Samsung Display Co., LTD.
    Inventors: Sang Yong NO, Hwa Rang LEE, Kwi Hyun KIM, Ji Yeon CHOI
  • Publication number: 20220378676
    Abstract: Disclosed herein is a composition for enhancing skin elasticity or improving skin wrinkles. In one aspect, 2-isopropylmalic acid or a salt, hydrate or solvate thereof, which is an active ingredient of the present disclosure, activates skin primary cilia and inhibits the expression of MMP-1 to enhance skin elasticity and improve skin wrinkles. In addition, in one aspect, 2-isopropylmalic acid or a salt, hydrate or solvate thereof, which is an active ingredient of the present disclosure, is a safe material and has the advantage that it can be treated in the living body in various forms such as cosmetics and food.
    Type: Application
    Filed: May 13, 2022
    Publication date: December 1, 2022
    Applicants: AMOREPACIFIC CORPORATION, KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Hyunjung CHOI, Dong-Hyung CHO, Ji-Eun BAE, Joonbum KIM, Ji Yeon CHOI, Daejin MIN, Hye Won NA, Hyoung June KIM, Wonseok PARK
  • Patent number: 11508178
    Abstract: A fingerprint sensor includes a substrate, a sensor pixel disposed on the substrate and including a light sensing element through which a sensing current flows according to an amount of incident light, a light-blocking conductive layer disposed on the sensor pixel and including a plurality of holes, a first fingerprint pad disposed on the substrate, and a conductive connector connected to the first fingerprint pad and to which a predetermined voltage is applied. The light-blocking conductive layer is electrically connected to the conductive connector.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeong Heon Lee, Young Sik Kim, Jung Hak Kim, Kyo Won Ku, Hee Yeon Choi
  • Publication number: 20220343824
    Abstract: A display device includes a data driver that outputs a first data signal and a second data signal of different voltages, and a pixel that emits light in response to the first data signal and the second data signal. The pixel includes a current generator generating a driving current corresponding to the first data signal, a first light emitting part including a first electrode, a second electrode, and a first light emitting element, a second light emitting part including a third electrode, a fourth electrode connected, and a second light emitting element, and a current controller controlling a divided current supplied to the second light emitting part in response to the second data signal.
    Type: Application
    Filed: December 8, 2021
    Publication date: October 27, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Kwi Hyun KIM, Sang Yong NO, Hwa Rang LEE, Ji Yeon CHOI
  • Patent number: 11468817
    Abstract: A display device includes a data driver that outputs a first data signal and a second data signal of different voltages, and a pixel that emits light in response to the first data signal and the second data signal. The pixel includes a current generator generating a driving current corresponding to the first data signal, a first light emitting part including a first electrode, a second electrode, and a first light emitting element, a second light emitting part including a third electrode, a fourth electrode connected, and a second light emitting element, and a current controller controlling a divided current supplied to the second light emitting part in response to the second data signal.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwi Hyun Kim, Sang Yong No, Hwa Rang Lee, Ji Yeon Choi
  • Publication number: 20220293052
    Abstract: Provided herein may be a pixel. The pixel may include a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power line, and a second electrode coupled to a second node, a control transistor including a gate electrode coupled to the first node, a first electrode coupled to the second node, and a second electrode that is different from the first electrode, a first emission unit including at least one light-emitting element coupled between the second electrode of the control transistor and a second power line, and a second emission unit including at least one light-emitting element coupled between the second node and the second power line, wherein the second electrode of the control transistor is coupled to a first electrode of the first emission unit.
    Type: Application
    Filed: November 5, 2021
    Publication date: September 15, 2022
    Inventors: Hwa Rang LEE, Kwi Hyun KIM, Sang Yong NO, Ji Yeon CHOI
  • Patent number: 11404955
    Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 2, 2022
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Chung Yuen Won, Kwang Su Na, Mi Na Kim, Bong Yeon Choi, Kyoung Min Kang, Hoon Lee, Chang Gyun An, Tae Gyu Kim, Jun Sin Yi
  • Publication number: 20220231079
    Abstract: A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver.
    Type: Application
    Filed: September 23, 2021
    Publication date: July 21, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Ki Yeup LEE, Sang Yong NO, Ji Yeon CHOI, Tae Ho KANG, Hwa Rang LEE
  • Publication number: 20220220345
    Abstract: The present technology is intended to provide an adhesive tape for a semiconductor package manufacturing process, which, in the process of manufacturing a semiconductor package having a plurality of protruding electrodes, may protect the bottom surface of the semiconductor package and the plurality of protruding electrodes formed on the bottom surface of the semiconductor package and may be easily removed from the semiconductor package without leaving residue behind after a given manufacturing process is completed.
    Type: Application
    Filed: October 30, 2019
    Publication date: July 14, 2022
    Applicant: MODU TECH CO., LTD.
    Inventors: Byeong Yeon CHOI, Seung Yol LEE, Suk Hee KANG, Gyung Ju YOON
  • Publication number: 20220190093
    Abstract: A display device, includes: pixels at a display area; gate lines at the display area, and connected to the pixels; carry clock lines and scan clock lines at the display area; and a gate driving circuit distributedly located at the display area, and connected to the carry clock lines, the scan clock lines, and the gate lines. The gate driving circuit includes a plurality of stages, each of the stages to output, as a carry signal, a carry clock signal supplied through a corresponding carry clock line from among the carry clock lines, and to output, as a scan signal, a scan clock signal supplied through a corresponding scan clock line from among the scan clock lines. The corresponding carry clock line and the corresponding scan clock line corresponding to one stage from among the stages are spaced from each other with at least one of the pixels interposed therebetween.
    Type: Application
    Filed: August 17, 2021
    Publication date: June 16, 2022
    Inventors: Sang Yong NO, Tae Ho KANG, Kwi Hyun KIM, Hwa Rang LEE, Ji Yeon CHOI
  • Publication number: 20220127677
    Abstract: The present invention relates to a technique in which a target exosome subpopulation, a sub-subpopulation, or a lower population in human fluid, which is associated with a specific disease, is isolated and recovered in its intact form at high yield to prepare a liquid biopsy sample and analyzed.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 28, 2022
    Applicant: SOL BIO CORPORATION
    Inventors: Sung-Ho PAEK, Da-Yeon CHOI
  • Publication number: 20220102476
    Abstract: Provided is a tiled display. The tiled display includes: a first display device including a first display area including pixels, a second display device including a second display area including pixels adjacent to the first display area, and a seam between the first display area and the second display area. Each of the first display device and the second display device includes: a first base part supporting a respective one of the first display device and the second display device, a thin-film transistor layer on the first base part, the thin-film transistor layer including thin-film transistors included in the pixels and including connection lines in the seam, and bridge electrodes in the seam to couple between the connection lines of the first display device and the second display device.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 31, 2022
    Inventors: Kwi Hyun KIM, Sang Yong NO, Tae Ho KANG, Hwa Rang LEE, Joon Hoo CHOI, Ji Yeon CHOI
  • Publication number: 20220091982
    Abstract: A battery management apparatus according to an embodiment of the present disclosure includes a processor including a plurality of cores respectively provided with a cache memory and configured to set a core storing a record-target data in the cache memory thereof among the plurality of cores as a main core and set a core other than the main core among the plurality of cores as a sub core; and a main memory configured to store the record-target data by the main core, wherein the main core is configured to block an authority of the sub core to access the main memory while the record-target data is being recorded in the main memory, and endow an authority to access the main memory to the sub core after the record-target data is recorded in the main memory.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 24, 2022
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Jae-Yeon CHOI, Jong-Shik BAEK
  • Publication number: 20220050317
    Abstract: A display device includes a first display panel for displaying a first image, a fingerprint sensor disposed on one surface of the first display panel and detecting light passing through the first display panel, and a first light transmission control unit disposed between the first display panel and the fingerprint sensor for controlling transmission of light.
    Type: Application
    Filed: April 20, 2021
    Publication date: February 17, 2022
    Inventors: Kyo Won Ku, Jung Hak Kim, Young Sik Kim, Jin Woo Kim, Jeong Heon Lee, Hee Yeon Choi
  • Publication number: 20220045601
    Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.
    Type: Application
    Filed: September 3, 2021
    Publication date: February 10, 2022
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Chung Yuen WON, Kwang Su NA, Mi Na KIM, Bong Yeon CHOI, Kyoung Min KANG, Hoon LEE, Chang Gyun AN, Tae Gyu KIM, Jun Sin YI
  • Publication number: 20220045599
    Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.
    Type: Application
    Filed: June 21, 2021
    Publication date: February 10, 2022
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Chung Yuen WON, Kwang Su NA, Mi Na KIM, Bong Yeon CHOI, Kyoung Min KANG, Hoon LEE, Chang Gyun AN, Tae Gyu KIM, Jun Sin YI