Patents by Inventor Yeonchoo CHO

Yeonchoo CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190294047
    Abstract: A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 26, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin SHIN, Sangwon KIM, Minsu SEOL, Seongjun PARK, Yeonchoo CHO
  • Publication number: 20190157211
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae SONG, Seunggeol Nam, Yeonchoo Cho, Seongjun Park, Hyeonjin Shin, Jaeho Lee
  • Publication number: 20190157212
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae SONG, Seunggeol NAM, Yeonchoo CHO, Seongjun PARK, Hyeonjin SHIN, Jaeho LEE
  • Patent number: 10229881
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae Song, Seunggeol Nam, Yeonchoo Cho, Seongjun Park, Hyeonjin Shin, Jaeho Lee
  • Patent number: 10217513
    Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Seunggeol Nam, Changhyun Kim, Hyeonjin Shin, Yeonchoo Cho, Jinseong Heo, Seongjun Park
  • Patent number: 10199469
    Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyeonjin Shin, Yeonchoo Cho, Minhyun Lee, Changhyun Kim, Seongjun Park
  • Publication number: 20180350915
    Abstract: A semiconductor device includes a substrate and a graphene layer. The substrate includes an insulator and a semiconductor. The graphene layer is grown on a surface of the semiconductor. The semiconductor includes at least one of a group IV material and a group III-V compound. A method of manufacturing the semiconductor device is disclosed.
    Type: Application
    Filed: November 8, 2017
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Keunwook SHIN, Hyeonjin Shin, Yeonchoo Cho, Seunggeol Nam, Seongjun Park, Yunseong Lee
  • Patent number: 10134628
    Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae Song, Seunggeol Nam, Seongjun Park, Keunwook Shin, Hyeonjin Shin, Jaeho Lee, Changseok Lee, Yeonchoo Cho
  • Patent number: 10133176
    Abstract: A hardmask composition includes a plurality of graphene nanosheets doped with boron (B) and/or nitrogen (N) and a solvent. A size of the graphene nanosheet may be in a range of about 5 nm to about 1000 nm. The hardmask composition may include an aromatic ring-containing material.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minsu Seol, Sangwon Kim, Hyeonjin Shin, Seongjun Park, Yeonchoo Cho
  • Publication number: 20180259844
    Abstract: A pellicle for a photomask, a reticle including the same, and an exposure apparatus for lithography are provided. The pellicle may include a pellicle membrane and a passivation member. The pellicle membrane may include a carbon-based material having defects. The passivation member may cover the defects of the carbon-based material. The passivation member may include an inorganic material. The passivation member may be disposed on one or two surfaces of the pellicle membrane. The pellicle for the photomask may be applied to extreme ultraviolet (EUV) lithography.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Hyunjae Song, Minhyun Lee, Yeonchoo Cho
  • Publication number: 20180061490
    Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 1, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minhyun LEE, Seunggeol NAM, Changhyun KIM, Hyeonjin SHIN, Yeonchoo CHO, Jinseong HEO, Seongjun PARK
  • Publication number: 20180047818
    Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).
    Type: Application
    Filed: February 22, 2017
    Publication date: February 15, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol NAM, Hyeonjin SHIN, Yeonchoo CHO, Minhyun LEE, Changhyun KIM, Seongjun PARK
  • Patent number: 9721943
    Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changseok Lee, Keunwook Shin, Hyeonjin Shin, Seongjun Park, Hyunjae Song, Hyangsook Lee, Yeonchoo Cho
  • Publication number: 20170033003
    Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.
    Type: Application
    Filed: June 3, 2016
    Publication date: February 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae SONG, Seunggeol NAM, Seongjun PARK, Keunwook SHIN, Hyeonjin SHIN, Jaeho LEE, Changseok LEE, Yeonchoo CHO
  • Publication number: 20160351491
    Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.
    Type: Application
    Filed: February 24, 2016
    Publication date: December 1, 2016
    Inventors: Changseok LEE, Keunwook SHIN, Hyeonjin SHIN, Seongjun PARK, Hyunjae SONG, Hyangsook LEE, Yeonchoo CHO
  • Publication number: 20160291472
    Abstract: A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.
    Type: Application
    Filed: September 2, 2015
    Publication date: October 6, 2016
    Inventors: Hyeonjin SHIN, Sangwon KIM, Minsu SEOL, Seongjun PARK, Yeonchoo CHO
  • Publication number: 20160282721
    Abstract: A hardmask composition includes a plurality of graphene nanosheets doped with boron (B) and/or nitrogen (N) and a solvent. A size of the graphene nanosheet may be in a range of about 5 nm to about 1000 nm. The hardmask composition may include an aromatic ring-containing material.
    Type: Application
    Filed: August 13, 2015
    Publication date: September 29, 2016
    Inventors: Minsu SEOL, Sangwon KIM, Hyeonjin SHIN, Seongjun PARK, Yeonchoo CHO
  • Publication number: 20160240482
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Application
    Filed: July 31, 2015
    Publication date: August 18, 2016
    Inventors: Hyunjae SONG, Seunggeol NAM, Yeonchoo CHO, Seongjun PARK, Hyeonjin SHIN, Jaeho LEE