Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

Abstract: A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

Abstract: A semiconductor device includes a substrate and a graphene layer. The substrate includes an insulator and a semiconductor. The graphene layer is grown on a surface of the semiconductor. The semiconductor includes at least one of a group IV material and a group III-V compound. A method of manufacturing the semiconductor device is disclosed.

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

Abstract: Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate.

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract: A pellicle for a photomask, a reticle including the same, and an exposure apparatus for lithography are provided. The pellicle may include a pellicle membrane and a passivation member. The pellicle membrane may include a carbon-based material having defects. The passivation member may cover the defects of the carbon-based material. The passivation member may include an inorganic material. The passivation member may be disposed on one or two surfaces of the pellicle membrane. The pellicle for the photomask may be applied to extreme ultraviolet (EUV) lithography.

Abstract: A method of growing graphene includes forming a carbon monolayer on a substrate by injecting a first reaction gas into a reaction chamber, wherein the first reaction gas includes a first source including a component that is a carbon source and belongs to an electron withdrawing group, and injecting a second reaction gas including a second source into the reaction chamber, wherein the second source includes a functional group that forms a volatile structure by reacting with a component that belongs to an electron withdrawing group. Graphene may be directly grown on a surface of the substrate by repeatedly injecting the first reaction gas and the second reaction gas.

Abstract: A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

Abstract: An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

Abstract: Provided are methods of directly growing a carbon material. The method may include a first operation and a second operation. The first operation may include adsorbing carbons onto a substrate by supplying the carbons to the substrate. The second operation may include removing unreacted carbon residues from the substrate after suspending the supplying the carbons of the first operation. The two operations may be repeated until a desired graphene is formed on the substrate. The substrate may be maintained at a temperature less than 700° C. In another embodiment, the method may include forming a carbon layer on a substrate, removing carbons that are not directly adsorbed to the substrate on the carbon layer, and repeating the two operations until desired graphene is formed on the substrate. The forming of the carbon layer includes supplying individual carbons onto the substrate by preparing the individual carbons.

Abstract: A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.