Abstract: A display device includes pixels arranged in a matrix form, gate lines extending in a first direction; data lines extending in a second direction, first and second unit pixel columns, each defined by adjacent data lines and the pixels connected thereto, first and second channels which transmit data signals to each of the first and second unit pixel columns, and a line selector which connects the first and second channels to the data lines and provides data voltages to the data lines in response to control signals, where a pixel connected to a first gate line is connected to a data line at a side thereof, a pixel connected to a second gate line is connected to a data line at the other side thereof, and each of the first and second channels is connected to a data line of each of the first and second unit pixel columns.

Abstract: A display apparatus includes a panel module displaying a 2-dimensional (2D) image or a 3-dimensional (3D) stereoscopic image, a lens panel disposed over the panel module and including a first substrate, a second substrate and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of first electrodes, a plurality of floating electrodes and a plurality of second electrodes, the floating electrodes partially overlapping with the first electrodes and being electrically floated, the second electrodes partially overlapping with the floating electrodes, and a light source module supplying light to the panel module.

Abstract: A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

Abstract: A display apparatus includes a substrate and a display area and a peripheral area on the substrate. The peripheral area is outside the display area, and a gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a first stage coupled to a first gate line and a second stage coupled to a second gate line, and the first stage and the second stage are configured as mirror images of each other.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

Abstract: A display apparatus includes a backlight assembly, a driving circuit part, and a display panel. The backlight assembly emits light. The driving circuit part receives an image signal, converts the image signal into image data, and generates a driving signal based on the image data. The display panel includes at least one pixel in which a plurality of sub-pixels is arranged in a two row by four column array, wherein the panel receives the light to display an image in response to the driving signal, wherein two sub-pixels of the sub-pixels arranged in a first row of the array each comprise a white color filter and two sub-pixels of the sub-pixels arranged in a second row of the array each comprise a white color filter.

Abstract: A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A display device includes: an insulation substrate; a plurality of gate lines on the insulation substrate and divided into a first group and a second group; a plurality of data lines insulated from and intersecting the gate lines; a gate driver which applies a gate-on voltage to the gate lines and operates in one of a first mode and a second mode; and a data driver which applies a data voltage to the data lines, where the first group and the second group of the gate lines are applied with the gate-on voltage when the gate driver is in the first mode, and where the first group of the gate lines is applied with the gate-on voltage and the second group of the gate lines is in an off state when the gate driver is in the second mode.

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.

Abstract: A liquid crystal display (“LCD”) has first, second, and third pixels adjacent to one another in a column direction. The LCD includes a first gate line connected to each of the second and third pixels in common, a capacitance electrode line connected to each of the first and second pixels in common, a first data line connected to the second pixel, and a second data line connected to the first and third pixels.

Abstract: A display apparatus includes a backlight assembly, a driving circuit part, and a display panel. The backlight assembly emits light. The driving circuit part receives an image signal, converts the image signal into image data, and generates a driving signal based on the image data. The display panel includes at least one pixel in which a plurality of sub-pixels is arranged in a two row by four column array, wherein the panel receives the light to display an image in response to the driving signal, wherein two sub-pixels of the sub-pixels arranged in a first row of the array each comprise a white color filter and two sub-pixels of the sub-pixels arranged in a second row of the array each comprise a white color filter.

Abstract: A display device includes pixels, gate lines, and data lines on a substrate. The pixels include sub-pixels, and each sub-pixel includes a respective one of a plurality of first electrodes connected to one of the gate lines and one of the data lines. The first electrode of the sub-pixel at an n-th row and the first electrode of the sub-pixel at an (n+2)-th row in a same column are connected to different ones of the data lines. The sub-pixels in the n-th and (n+2)-th rows in the same column emit the same color of light.

Abstract: A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A three-dimensional (3D) image display device includes data lines, gate lines crossing the data lines, sub-pixels arranged in areas between the data lines and the gate lines, a data driver that drives the data lines, a first gate driver that drives first gate lines from among the gate lines, a second gate driver that drives second gate lines from among the gate lines, and a timing controller that controls the data driver, the first gate driver, and the second gate drivers according to an image signal and a control signal. The second gate driver does not drive the second gate lines during a 3D display mode.

Abstract: A display substrate includes thin film transistors, first common voltage lines, and second common voltage lines. Each thin film transistor includes a gate electrode, a source electrode, and an annulus-shaped drain electrode. The first common voltage lines are disposed adjacent to first sides of the gate electrodes. The second common voltage lines are disposed adjacent to second sides of the gate electrodes.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.