Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: In a liquid crystal display one pixel is divided into two subpixels, the two subpixels are connected to two subdata lines extending from one data line, and a desired data voltage is applied by using a data driving switching element connected to the subdata line, thereby reducing the number of data lines needed to reduce the cost of the driver and preventing a lack of space to mount the data driver while dividing one pixel into two subpixels and differently applying voltages of the two subpixels.

Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

Abstract: A display substrate includes a first storage line, a second storage line, a first data line, a second data line, a storage electrode, a first sub-storage electrode and a second sub-storage electrode. The first storage line is extended in a first direction. The second storage line is spaced apart from and parallel to the first storage line. The first data line is extended in a second direction. The second data line is spaced apart from and parallel to the first data line. The storage electrode is connected to the first and second storage lines, and extended in the second direction. The storage electrode is disposed on an interval area between the first and second data lines. The first sub-storage electrode is overlapped with a first area of the storage electrode. The second sub-storage electrode is overlapped with a second area of the storage electrode.

Abstract: A liquid crystal display includes a substrate including a longer first side and a shorter second side, a plurality of gate lines disposed on the substrate, a plurality of data lines disposed on the substrate perpendicular to and insulated from the gate lines, and a plurality of pixel electrodes, each pixel electrode electrically connected to a data line by a switching element, wherein a number of the gate lines is about half of a number of the pixel electrodes, and the data lines extend in a direction which is substantially parallel to a direction of the first side.

Abstract: A gate driving circuit includes a plurality of stages outputting gate signals to a plurality of gate lines. Each of the stages includes a circuit transistor, a capacitor part, a first connecting electrode and a second connecting electrode. The circuit transistor outputs the gate signal to an output electrode in response to a control signal inputted to a control electrode. The capacitor part is disposed adjacent to the circuit transistor, and includes a first electrode, a second electrode disposed over the first electrode, a third electrode disposed over the second electrode and a fourth electrode disposed over the third electrode. The first connecting electrode electrically connects the control electrode to the first and third electrodes. The second connecting electrode electrically connects the output electrode to the second and fourth electrodes.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: An exemplary embodiment of the present invention provides a liquid crystal display including: a first insulating substrate; a light blocking member positioned on the first insulating substrate and having a frame portion defining openings for pixels; a step compensated pattern positioned on the first insulating substrate and in one of the openings; a second insulating substrate facing the first insulating substrate; a first electrode formed on the first insulating substrate in the same layer as a second domain dividing unit; a second electrode facing the first electrode and disposed in the same layer as the first domain dividing unit; and a liquid crystal layer interposed between the first electrode and the second electrode, wherein the step compensated pattern overlaps the first domain dividing unit or the second domain dividing unit.

Abstract: A liquid crystal display according to an embodiment of the present invention includes: a first substrate; a plurality of color filters formed on the first substrate and arranged in a matrix with an island shape; a plurality of pixel electrodes formed on the color filters; and a capacitor disposed between neighboring color filters in a column direction among the color filters, wherein two terminals forming the capacitor are disposed at a portion outside a position overlapping the color filters.

Abstract: A three-dimensional (3D) image display device includes data lines, gate lines crossing the data lines, sub-pixels arranged in areas between the data lines and the gate lines, a data driver that drives the data lines, a first gate driver that drives first gate lines from among the gate lines, a second gate driver that drives second gate lines from among the gate lines, and a timing controller that controls the data driver, the first gate driver, and the second gate drivers according to an image signal and a control signal. The second gate driver does not drive the second gate lines during a 3D display mode.

Abstract: A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.