Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A magnetic memory element utilizing spin transfer switching includes a pinned layer, a tunneling barrier layer and a free layer structure. The tunneling barrier layer is disposed on the pinned layer. The free layer structure includes a composite free layer. The composite free layer includes a first free layer, an insert layer and a second free layer. The first free layer is disposed on the tunneling barrier layer and has a first spin polarization factor and a first saturation magnetization. The insert layer is disposed on the first free layer. The second free layer is disposed on the insert layer and has a second spin polarization factor smaller than the first spin polarization factor and a second saturation magnetization smaller than the first saturation magnetization. Magnetization vectors of the first free layer and the second free layer are arranged as parallel-coupled.

Abstract: A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to the first transistor, a second transmission gate electrically connected to the first and third transistors, a comparison circuit having two input ends respectively connected to the first transistor, and a storage capacitor having an end electrically connected to the first transistor and the other end connected to a power end.

Abstract: A magnetic random access memory (MRAM) including multiple memory cells for forming an array is provided. Each memory cell has a magnetic free stack layer and a pinned stack layer. A magnetization of the pinned stack layer is set toward a predetermined direction. The magnetic free stack layer has a magnetic easy axis. Two magnetic easy axes of adjacent two memory cells are substantially perpendicular to each other.

Abstract: A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A structure of magnetic memory cell including a first anti-ferromagnetic layer is provided. A first pinned layer is formed over the first anti-ferromagnetic layer. A tunneling barrier layer is formed over the first pinned layer. A free layer is formed over the tunneling barrier layer. A metal layer is formed over the free layer. A second pinned layer is formed over the metal layer. A second anti-ferromagnetic layer is formed over the second pinned layer.

Abstract: A magnetic memory includes a stack, a first writing wire, and a second writing wire. The stack includes a magnetic pinned layer, a tunnel barrier insulating layer, and a magnetic free layer, so as to form a magnetic tunnel junction (MTJ). The MTJ has an easy axis. The first writing wire is disposed under the stack. The included angle between the first writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on a projected plane. The second writing wire is disposed above the stack. The included angle between the second writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on the projected plane.

Abstract: A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to the first transistor, a second transmission gate electrically connected to the first and third transistors, a comparison circuit having two input ends respectively connected to the first transistor, and a storage capacitor having an end electrically connected to the first transistor and the other end connected to a power end.

Abstract: A magnetic memory including a stack, a first writing wire, and a second writing wire is provided. The stack includes a magnetic pinned layer, a tunnel barrier insulating layer, and a magnetic free layer, so as to form a magnetic tunnel junction (MTJ). The MTJ has an easy axis. The first writing wire is disposed under the stack. The included angle between the first writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on a projected plane. The second writing wire is disposed above the stack. The included angle between the second writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on the projected plane.

Abstract: The present invention provides an optical head with a single or multiple sub-wavelength light beams, which can be used in arenas such as photolithography, optical storage, optical microscopy, to name a few. The present invention includes a transparent substrate, a thin film, and a surface structure with sub-wavelength surface profile. The incident light transmits through the transparent substrate, forms a surface plasma wave along the sub-wavelength aperture located within the thin film, and finally re-emits through spatial coupling with the sub-wavelength profile of the surface structure. As the coupled re-emitting light beam or light beams can maintain the waist less than that of the diffraction limit for a few micrometers out of the surface with sub-wavelength profile in many cases, this invention can have applications ranging from micro or nano manufacturing, metrology, and manipulation by using light beams with waist smaller than the diffraction limit.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A method of accessing a shared memory store at a multiported data network node is provided. The method provides for a deterministic access schedule to be used in apportioning processing bandwidth between data ports and bus connected devices used in processing conveyed data. Advantages are derived from eliminating data processing latencies otherwise incurred from: data bus arbitration related to handshaking, arbitration request processing, and switching between read and write memory access cycles.

Abstract: A method of controlling the build-up of organic and/or inorganic contaminants (e.g., carbonates, nitrates, nitrites, and the like) in an aqueous process stream, comprising directing at least some of the contaminated stream to a heating means wherein at least some of the contaminants are decomposed. Thereafter, the decomposition products are removed and the purified stream is returned to the process. In a preferred embodiment, the process is an alkylene oxide manufacturing process, and the contaminated aqueous stream is the effluent from a catalyzed scrubbing system for removal of carbon dioxide. Organic contaminants are decomposed to carbon dioxide, which is flashed off; inorganic salts which are decomposed to gases are flashed off; inorganic salts which are not converted to gases are scrubbed out.