Abstract: Provided are a semiconductor structure and a preparation method therefor. The semiconductor structure includes a substrate, a support structure, capacitor holes penetrating the support structure, and capacitor structures formed by filling the capacitor holes. The support structure includes a first support layer, and the first support layer includes first sub-holes and second sub-holes. The first sub-holes are distributed on an edge of an array region and surround the second sub-holes located inside the array region, and a projection area of each of the first sub-holes on a plane of the substrate is less than a projection area of each of the second sub-holes on the plane of the substrate.

Abstract: A semiconductor structure includes a substrate and a first bit line pillar. The first bit line pillar is located on the substrate, and includes a first dielectric layer, a first insulating layer, and a first contact layer that are successively stacked in a thickness direction of the substrate. The first insulating layer is adjacent to the substrate and has a first preset thickness. The first preset thickness is associated with a thickness sum of the first dielectric layer, the first insulating layer, and the first contact layer. A ratio of a length of a top surface of the first insulating layer in a first direction to a length of a bottom surface of the first insulating layer in the first direction is a first target value. The first direction, the top surface and the bottom surface of the first insulating layer are all perpendicular to the thickness direction.

Abstract: A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Abstract: Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.

Abstract: A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

Abstract: A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.

Abstract: This application provides a method for manufacturing a memory and a memory thereof. The manufacturing method includes: providing a substrate, where the substrate includes a plurality of spaced active area and each of the plurality of spaced active area includes a first contact region and a second contact region; forming a plurality of spaced bit lines on the substrate, where each of the plurality of spaced bit lines is connected to at least one first contact region; forming a first isolation layer on each of the plurality of spaced bit lines, a first trench extending in a first direction between two adjacent first isolation layers of the plurality of spaced bit lines; etching a bottom along the first trench to form a second trench; and forming a plurality of conducting wires and a plurality of second isolation layers in the second trench.

Abstract: A method for manufacturing a memory includes: providing a substrate having a core region provided with a word line; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on a hole wall of the first filling hole, where the barrier layer located in the first filling hole surrounds and forms a first intermediate hole exposing the word line; etching the word line exposed in the first intermediate hole to remove a first residue on the word line; and forming in the first intermediate hole a first wire electrically connected to the word line.

Abstract: The present application provides a method for fabricating a semiconductor memory structure. The method includes: providing a substrate; forming a stack layer on the substrate, and arranging spacer rows in the stack layer, forming a plurality of active lines, and forming a plurality of transfer pillars in the stack layer; forming a spacer structure outside the transfer pillars, and forming an etching hole; etching the second composite mask layer and the initial semiconductor along the etching hole layer of the active lines to form a plurality of discrete active region masks; and etching the substrate along the active region masks to form a plurality of discrete active regions. The disclosed technique can effectively reduce the preparation difficulty of the active area, improve the LCDU of the active area, and improve the performance of the semiconductor structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

Abstract: The present application provides a semiconductor structure and a preparation method thereof, including: a substrate; a trench; a bit line contact structure; a bit line structure; a bit line protection structure, the bit line protection structure including a top dielectric layer and a sidewall structure, the top dielectric layer is located on the bit line structure and forms a laminated structure together with the bit line structure; the sidewall structure covers part of sidewalls of the laminated structure on the substrate, the sidewall structure has a first air gap; an isolation pattern structure, the isolation pattern structure has a second air gap, the isolation pattern structure extends along a second direction, the second direction intersects with the first direction, to form capacitance contact hole between the adjacent bit line protection structures and the adjacent isolation pattern structures.

Abstract: The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.

Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.

Abstract: The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.

Abstract: A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

Abstract: Provided is a semiconductor structure and a method for manufacturing the same. The method includes forming a spin on hard mask layer on a base, active areas arranged at intervals in the base, bit lines arranged at intervals and extending in a first direction on the base, each bit line electrically connected to at least one active area, and the spin on hard mask layer filled between the bit lines and covering the bit lines; removing part of the spin on hard mask layer to form first trenches arranged at intervals and extending in a second direction; forming first sacrificial layers in the first trenches; removing the spin on hard mask layer between the first sacrificial layers to form second trenches; forming first supporting layers in the second trenches; removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.