Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a gate trench in the substrate, the gate trench including a first trench and a second trench, the second trench being located above the first trench, communicating with the first trench, and having a width greater than a width of the first trench; and forming a gate word line in the gate trench.

Abstract: This application provides a method for manufacturing a memory and a memory thereof. The manufacturing method includes: providing a substrate, where the substrate includes a plurality of spaced active area and each of the plurality of spaced active area includes a first contact region and a second contact region; forming a plurality of spaced bit lines on the substrate, where each of the plurality of spaced bit lines is connected to at least one first contact region; forming a first isolation layer on each of the plurality of spaced bit lines, a first trench extending in a first direction between two adjacent first isolation layers of the plurality of spaced bit lines; etching a bottom along the first trench to form a second trench; and forming a plurality of conducting wires and a plurality of second isolation layers in the second trench.

Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.

Abstract: A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

Abstract: A method of forming a semiconductor memory includes: providing comprising a storage area and a peripheral area located outside the storage area, wherein the substrate has and a plurality of bit line contact parts and a plurality of capacitor contact parts located in the storage area, and a peripheral gate contact part and a peripheral circuit contact part located in the peripheral area; forming a plurality of bit lines, and simultaneously forming a peripheral gate; forming a bit line isolation layer, and simultaneously forming a peripheral gate isolation layer; forming a first conductive capacitor layer in contact with the capacitor contact part, and simultaneously forming a first peripheral conductive layer in contact with the peripheral circuit contact part; forming a first air gap in the bit line isolation layer, and simultaneously forming a second air gap in the peripheral gate isolation layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.