Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for generating and transmitting autonomous vehicle prepositioning instructions to improve network coverage. In particular, in one or more embodiments, the disclosed systems subdivide a geographic transportation service area into subregions, generate a set of waypoints and circuits for the subregions. Moreover, in one or more embodiments, the disclosed systems utilize an optimization model to assign autonomous vehicles to the set of waypoints and circuits and transmit digital prepositioning instructions to the autonomous vehicles to traverse the waypoints and circuits.

Abstract: A package structure is provided. The package structure includes a lower semiconductor die and a first protective layer surrounding the lower semiconductor die. The package structure also includes a dielectric layer partially covering the first protective layer and the lower semiconductor die and an upper semiconductor die over the lower semiconductor die and the first protective layer. The upper semiconductor die is bonded with the lower semiconductor die through a connector. The package structure further includes an insulating film surrounding the connector and a second protective layer surrounding the upper semiconductor die. A portion of the second protective layer is between the insulating film and the dielectric layer.

Abstract: A power conversion device used in electric vehicles includes a transmission assembly and a power converter. The transmission assembly is detachably connected to the electric vehicle and receives a first power from the battery pack of the electric vehicle. The power converter is electrically connected to the transmission assembly and converts the first power into a second power or a third power. The power converter is configured outside the electric vehicle.

Abstract: A solar energy optimization device, a solar energy generation system and a power conversion system using the same are provided. The solar energy optimization device includes a plurality of conversion circuits and a plurality of control circuits. Each of conversion circuits is individually connected in series with a solar module. The conversion circuits and the solar modules are connected in series to a maximum power point tracking (MPPT) circuit. The MPPT circuit is configured to determine a photovoltaic current according to the solar modules. Each of the conversion circuits is used for converting a photovoltaic voltage of one of the solar modules into an output voltage. Each of the control circuits is used to adjust a conversion parameter of one of the conversion circuits to increase the output voltage thereof, so that an output power of each of the solar modules is optimized based on the photovoltaic current.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. The through via is disposed outside of and adjacent to the second semiconductor die. The through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.

Abstract: A display device, characterized in that the display device includes a first panel, having a first side and a first light shielding layer at a periphery of the first panel, wherein the first light shielding layer has a first edge departing away from the first side; and a second panel, disposed on the first panel, and having a second side adjacent to the first side; wherein the second panel includes a second light shielding layer at a periphery of the second panel; and the second light shielding layer has a second edge departing away from the second side. Wherein a first width is measured from the first side to the first edge along a direction, a second width is measured from the second side to the second edge along the direction, the second width is greater than the first width, and the direction is vertical to the first side.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: An apparatus for fabricating an internally finned pressure vessel includes a plurality of positioning discs, each of the positioning discs defining a plurality of circumferentially spaced slots extending radially into the positioning disc from a perimeter thereof, and one or more rods extending through the plurality of positioning discs, the plurality of positioning discs being held in axial alignment by the one or more rods. A method of fabricating the internally finned pressure vessel includes providing the apparatus, loading a plurality of fins into the slots of the positioning discs, inserting the apparatus containing the plurality of fins into a pressure vessel, attaching the plurality of fins to the pressure vessel by a brazing process, and removing the apparatus from the pressure vessel.

Abstract: A method performed by at least one processor of an encoder comprises: performing, on an input 3D mesh, a symmetry detection process to estimate a partition plane. The method further comprises partitioning the input 3D mesh into a first side and a second side based on the partition plane, where the first side is opposite to the second side, and where a first vertex on the first side is symmetric to a second vertex on the second side. The method further comprises quantizing the first vertex and the second vertex in pairs to reduce a quantization error and symmetry prediction error associated with the first vertex and the second vertex.

Abstract: A method for extracting carbon dioxide from a flue gas includes a preparing process, an acid removing process, and a purifying and liquefying process. The preparing process is implemented by collecting the flue gas generated by oxygen-enriched combustion of a glass raw material with methane from a glass furnace. The flue gas includes the carbon dioxide, nitrogen, water vapor, oxygen, fluoric acid compounds, and boric acid compounds. The acid removing process is implemented by performing a first acid removing operation. The first acid removing operation is implemented by using a sodium hydroxide aqueous solution to remove the fluoric acid compounds and the boric acid compounds in the flue gas. The purifying and liquefying process is implemented by using a purifying and liquefying unit to extract the flue gas that already undergoes the acid removing process, so as to obtain liquid carbon dioxide having a purity greater than 99%.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.

Abstract: A backlight module is provided and includes a side wall, a cushion member, and a light guide plate. The cushion member has a base portion and a side portion extending from the base portion, and the side portion abuts against the side wall, and the light guide plate is mounted on the cushion member. A display device is provided and includes the aforementioned backlight module, using the cushion member to support the light guide plate.

Abstract: A jujube harvesting apparatus with adjustable suction vector includes: an air duct assembly, where one end of which is arranged with an air duct inlet; a wind power device arranged on one end of the air duct assembly deviating from the air duct inlet and connected to the air duct assembly, where the wind power device is used for generating wind power; an ionization device arranged on the air duct assembly and positioned between the air duct inlet and the wind power device, where the ionization device is used for ionizing air in the air duct assembly to generate plasma; a magnetic field generating device including a first strip-shaped permanent magnet and a second strip-shaped permanent magnet; and a suction vector adjustable device including two moving assemblies, two rotating assemblies, an electromagnetic sensor component, and a control module.

Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.