Abstract: A method and apparatus comprising computer code configured to cause a processor or processors to generate more than one sub-mesh from an input mesh using one or more cutting planes. The processors may also encode the more than one sub-mesh in a bitstream, the more than one sub-mesh being encoded using different quantization parameters, and encode connectivity information according to the more than one sub-mesh in the bitstream using at least one header in the bitstream. The processors may the transmit the bitstream over a network.

Abstract: A die-transfer tool includes a source frame stage, a target frame stage, a roller, and a driving mechanism. The source frame stage is configured to secure a first tape. The target frame stage is configured to secure a second tape, wherein the second tape has an adhesive surface facing the source frame stage when the second tape is mounted on the target frame stage. The roller is configured to move laterally over the non-adhesive surface of the second tape opposite the adhesive surface when a plurality of dies is between the first tape and the adhesive surface of the second tape. The driving mechanism is configured to vertically drive the target frame stage to adjust the relative position of the target frame stage above the source frame stage.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: A method performed by at least one processor of an encoder comprises: performing, on an input 3D mesh, a symmetry detection process to estimate a partition plane. The method further comprises partitioning the input 3D mesh into a first side and a second side based on the partition plane, where the first side is opposite to the second side, and where a first vertex on the first side is symmetric to a second vertex on the second side. The method further comprises quantizing the first vertex and the second vertex in pairs to reduce a quantization error and symmetry prediction error associated with the first vertex and the second vertex.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: A transformer includes a bobbin and a plurality of coils wound on the bobbin. The plurality of coils includes a first primary coil; a second primary coil, located above the first primary coil and electrically connected to the first primary coil; a secondary coil, located between the first primary coil and the second primary; a first auxiliary coil, located above the second primary coil; and a second auxiliary coil, located on the first auxiliary coil and electrically connected to the first auxiliary coil.

Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.

Abstract: A power conversion device used in electric vehicles includes a transmission assembly and a power converter. The transmission assembly is detachably connected to the electric vehicle and receives a first power from the battery pack of the electric vehicle. The power converter is electrically connected to the transmission assembly and converts the first power into a second power or a third power. The power converter is configured outside the electric vehicle.

Abstract: A power conversion device includes a conversion device having includes a first, a second, a third and a fourth converter, and a control unit. The first converter has a first input terminal and a first output terminal; the second converter has a second input terminal and a second output terminal; the first and the second input terminal are electrically connected to a power supply. The third converter has a third input terminal and a third output terminal, the third input terminal is coupled to the first output terminal; the fourth converter has a fourth input terminal and a fourth output terminal; the fourth input terminal is coupled to the second output terminal, and the third output terminal is electrically connected to the fourth output terminal. The control unit is coupled to the conversion device, receives a power request from a load, and controls an output power of the conversion device.

Abstract: A semiconductor structure includes a first channel layer and a first barrier layer on the first channel layer. The first channel layer has a first potential well adjacent to the interface between the first channel layer and the first barrier layer. The semiconductor structure further includes a second channel layer on the first barrier layer, a second barrier layer on the second channel layer, and an intermediate layer between the second channel layer and the second barrier layer. The second channel layer has a second potential well adjacent to the interface between the second channel layer and the intermediate layer. The intermediate layer has a greater energy gap than either the first barrier layer or the second barrier layer. The energy gap of the first barrier layer is no less than the energy gap of the second barrier layer.

Abstract: Method, apparatus, and system for merging multiple attribute maps for mesh compression may be provided. The process may include obtaining multiple attribute maps associated with a mesh including one or more texture maps. The multiple attribute maps may be concatenated into a single concatenated map and concatenated UV coordinates for each of the multiple attribute maps may be generated based on re-computing original UV coordinates of each of the multiple attribute maps within the single concatenated map.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: The present disclosure provides a power conversion device. The power conversion device includes the multi-level power factor correction circuit, the at least one output capacitor, the at least one input capacitor group, the first resonant conversion circuit and the second resonant conversion circuit. The at least one input capacitor group includes the first input capacitor and the second input capacitor. The at least one output capacitor is connected to an output part of the multi-level power factor correction circuit. The at least one input capacitor group is connected to the at least one output capacitor in parallel. The second input capacitor is connected to the first input capacitor in series. The input part of the first resonant conversion circuit is connected to first input capacitor in parallel. The input part of the second resonant conversion circuit is connected to the second input capacitor in parallel.

Abstract: A remanufacturing method of a drill includes providing a drill with a worn-out area. The drill comprises: a shank part; and a flute part arranged on one end of the shank part. A chisel edge is formed on the front end of the flute part, and the radius of any one of the cross section of the chisel edge is defined as a core thickness; a first blade and a second blade with tilt directions toward the shank part are formed on the two sides of the chisel edge. The first circumferential surface of the first blade and the second circumferential surface of the second blade are respectively extended and spiraled toward the shank part along a periphery of the flute part and form two helical cutting edges, a first debris-discharging groove and a second debris-discharging groove. The first blade comprises a first cutting edge. The first cutting edge and the first circumferential surface define the worn-out area.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.