Patents by Inventor Yi Chao
Yi Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087964Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
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Patent number: 11927887Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.Type: GrantFiled: June 16, 2021Date of Patent: March 12, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guo-Xin Hu, Yuh-Kwei Chao, Chung-Yi Chiu
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Publication number: 20240065765Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Alvin Chao-Yu CHEN, Yi-Sheng CHAN, Chi-Pin HSU, Shang-Chih LIN, Chin-Ju WU, Jeng-Ywan JENG
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Patent number: 11915937Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.Type: GrantFiled: July 16, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Mao-Lin Huang, Lung-Kun Chu, Huang-Lin Chao, Chi On Chui
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Patent number: 11901426Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.Type: GrantFiled: December 16, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11894765Abstract: The present disclosure provides a power conversion device. The power conversion device includes the multi-level power factor correction circuit, the at least one output capacitor, the at least one input capacitor group, the first resonant conversion circuit and the second resonant conversion circuit. The at least one input capacitor group includes the first input capacitor and the second input capacitor. The at least one output capacitor is connected to an output part of the multi-level power factor correction circuit. The at least one input capacitor group is connected to the at least one output capacitor in parallel. The second input capacitor is connected to the first input capacitor in series. The input part of the first resonant conversion circuit is connected to first input capacitor in parallel. The input part of the second resonant conversion circuit is connected to the second input capacitor in parallel.Type: GrantFiled: June 16, 2022Date of Patent: February 6, 2024Assignee: Delta Electronics (Shanghai) Co., Ltd.Inventors: Yi-Chao Wang, Kai Dong, Shuai-Lin Du, Jin-Fa Zhang
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Patent number: 11890714Abstract: A remanufacturing method of a drill includes providing a drill with a worn-out area. The drill comprises: a shank part; and a flute part arranged on one end of the shank part. A chisel edge is formed on the front end of the flute part, and the radius of any one of the cross section of the chisel edge is defined as a core thickness; a first blade and a second blade with tilt directions toward the shank part are formed on the two sides of the chisel edge. The first circumferential surface of the first blade and the second circumferential surface of the second blade are respectively extended and spiraled toward the shank part along a periphery of the flute part and form two helical cutting edges, a first debris-discharging groove and a second debris-discharging groove. The first blade comprises a first cutting edge. The first cutting edge and the first circumferential surface define the worn-out area.Type: GrantFiled: July 1, 2021Date of Patent: February 6, 2024Assignee: TCT GLOBAL LIMITEDInventors: Chia Li Tao, Nick Sung-Hao Chien, Li-Yi Chao, Chen-Kuang Sun, Cheng Chia Lee, Ming-Yuan Zhao
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Patent number: 11888049Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.Type: GrantFiled: December 8, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Hong Chang, Yuan-Ching Peng, Chung-Ting Ko, Kuo-Yi Chao, Chia-Cheng Chao, You-Ting Lin, Chih-Chung Chang, Yi-Hsiu Liu, Jiun-Ming Kuo, Sung-En Lin
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Publication number: 20240030867Abstract: A solar energy optimization device, a solar energy generation system and a power conversion system using the same are provided. The solar energy optimization device includes a plurality of conversion circuits and a plurality of control circuits. Each of conversion circuits is individually connected in series with a solar module. The conversion circuits and the solar modules are connected in series to a maximum power point tracking (MPPT) circuit. The MPPT circuit is configured to determine a photovoltaic current according to the solar modules. Each of the conversion circuits is used for converting a photovoltaic voltage of one of the solar modules into an output voltage. Each of the control circuits is used to adjust a conversion parameter of one of the conversion circuits to increase the output voltage thereof, so that an output power of each of the solar modules is optimized based on the photovoltaic current.Type: ApplicationFiled: May 25, 2023Publication date: January 25, 2024Inventor: Yi-Chao FAN
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Patent number: 11862523Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.Type: GrantFiled: March 28, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
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Patent number: 11855154Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.Type: GrantFiled: August 3, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
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Patent number: 11856745Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.Type: GrantFiled: July 8, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
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Publication number: 20230383397Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yi-Lin WANG, Chin-Szu LEE, Hua-Sheng CHIU, Yi-Chao CHANG, Zih-Shou MUE
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Publication number: 20230387251Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
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Patent number: 11827970Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.Type: GrantFiled: May 5, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Wang, Chin-Szu Lee, Hua-Sheng Chiu, Yi-Chao Chang, Zih-Shou Mue
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Publication number: 20230377915Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Wei-Fu Wang, Yi-Chao Yi-Chao, Li-Ting Wang, Yee-Chia Yeo
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Publication number: 20230369495Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
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Publication number: 20230343712Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Patent number: D1002695Type: GrantFiled: June 15, 2022Date of Patent: October 24, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Chun-Yi Chao, Tzu-Min Yi, Po-Yen Tseng
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Patent number: D1002696Type: GrantFiled: June 15, 2022Date of Patent: October 24, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Chun-Yi Chao, Tzu-Min Yi, Po-Yen Tseng