Patents by Inventor Yi Chao

Yi Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Light emitting apparatus having antenna located in accommodation space formed by housing and control module
    Patent number: 11313518
    Abstract: A light emitting apparatus includes a housing, a connector, a light source, a control module board, and an antenna. The housing includes an inner space. The light source is located in the inner space. The control module board is located in the connector, wherein an accommodation space is formed by the housing and the control module board. The antenna is located in the accommodation space.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: April 26, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Sheng-Bo Wang, Chang-Hsieh Wu, Yi-Chao Lin, Yao-Zhong Liu, Jai-Tai Kuo
  • Dielectric Fin Structure
    Publication number: 20220115530
    Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
  • DETECTION DEVICE
    Publication number: 20220099586
    Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.
    Type: Application
    Filed: November 26, 2020
    Publication date: March 31, 2022
    Inventors: JING-ZHI HOU, LIN-HUI CHENG, YAN-CHAO MA, JIN-CAI ZHOU, ZI-LONG MA, NENG-NENG ZHANG, YI CHEN, CHEN-XI TANG, MENG LU, PENG ZHOU, LING-HUI ZHANG, LU-HUI FAN, SHI-GANG XU, CHENG-YI CHAO, LIANG-YI LU
  • VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE
    Publication number: 20220093456
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 24, 2022
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • Method for forming fin field effect transistor (FINFET) device structure with conductive layer between gate and gate contact
    Patent number: 11271112
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Kuo-Yi Chao, Rueijer Lin, Chen-Yuan Kao, Mei-Yun Wang
  • KEYBOARD DEVICE CAPABLE OF PRODUCING MULTI-ZONE LIGHTING EFFECT AND ILLUMINATION MODULE THEREOF
    Publication number: 20220035416
    Abstract: A keyboard device includes a keyboard module and an illumination module. The keyboard module includes plural first keys and at least one second key. The illumination module includes a light guide plate and a circuit board. The light guide plate includes plural first mapping zones and a second mapping zone. The first mapping zones are located under the corresponding first keys. The second mapping zone is located under the second key. Moreover, at least one side-view light-emitting element and at least one top-view light-emitting element are installed on the circuit board. The side-view light-emitting element emits a first light beam. The top-view light-emitting element emits a second light beam. The first light beam is extracted through the corresponding first mapping zone and transferred to the corresponding first key. The second light beam is transferred to the second key.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 3, 2022
    Inventors: Ding-Hsiang Pan, Hui-Ling Lin, Yi-Chao Huang
  • Structure and formation method of package structure with stacked semiconductor dies
    Patent number: 11239180
    Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a first semiconductor die over a carrier substrate and forming a first protective layer to surround the first semiconductor die. The method also includes forming a dielectric layer over the first protective layer and the first semiconductor die. The method further includes patterning the dielectric layer to form an opening partially exposing the first semiconductor die and the first protective layer. In addition, the method includes bonding a second semiconductor die to the first semiconductor die after the opening is formed. The method includes forming a second protective layer to surround the second semiconductor die.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Methods of forming air spacers in semiconductor devices
    Patent number: 11227950
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Conductive features having varying resistance
    Patent number: 11227830
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Via-first process for connecting a contact and a gate electrode
    Patent number: 11189525
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • OPERATION MONITORING SYSTEM AND MONITORING METHOD
    Publication number: 20210360846
    Abstract: An operation monitoring system and monitoring method are provided, the operation monitoring system is used for monitoring at least one agricultural machine, so as to control an operating range of the agricultural machine, the operation monitoring system includes a storage device and a processor, the processor recognizes at least one operating area and at least one non-operating area of an operation environment, and generates at least one boundary between the operating area and the non-operating area, the processor further generates least one electronic fence at the at least one boundary, the processor further acquires the position of the electronic fence and monitors a position of the agricultural machine, so as to monitor whether the agricultural machine is operating in the operating area on a side of the electronic fence, thereby controlling the operating range of the agricultural machine.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 25, 2021
    Inventors: SHUO QIN, Jia-yuan Qi, BING XU, YI-CHAO WU
  • VERTICAL INTERCONNECT FEATURES AND METHODS OF FORMING
    Publication number: 20210367043
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Contact formation method and related structure
    Patent number: 11177212
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • SYSTEM FOR THINNING SUBSTRATE
    Publication number: 20210335629
    Abstract: A system for thinning a substrate includes a chuck and a first liquid supply unit. The chuck includes a base portion and a frame portion disposed on the base portion, where the substrate is configured to be placed on a carrying surface of the chuck. The first liquid supply unit extends along sidewalls the frame portion and the base portion, an outlet of the first liquid supply unit is disposed next to the carrying surface of the chuck, the first liquid supply unit delivers a first liquid from a bottom of the chuck to the outlet, and the first liquid discharges from the outlet to cover a sidewall of the substrate.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • CONTACT FORMATION METHOD AND RELATED STRUCTURE
    Publication number: 20210320061
    Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: Po-Yu HUANG, Shih-Che LIN, Chao-Hsun WANG, Kuo-Yi CHAO, Mei-Yun WANG
  • Low-resistance interconnect structures
    Patent number: 11127684
    Abstract: A contact structure of a semiconductor device includes a gate contact in contact with a gate structure and extending through a first dielectric layer, a source/drain contact in contact with a source/drain feature and extending through the first dielectric layer, a common rail line in contact with the gate contact and the source/drain contact, and a power rail line in contact with the common rail line and electrically coupled to a ground of the semiconductor device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang, Ru-Gun Liu
  • DEBRANCHING ENZYME MODIFIED STARCH, THE PREPARING METHOD AND USE THEREOF IN HARD CAPSULE PRODUCTION
    Publication number: 20210275675
    Abstract: The present invention relates to a modified starch and a method for obtaining the modified starch by using a debranching enzyme, such as isoamylase, pullulanase, limit dextrinase and the like. The debranching enzyme modified starch of present invention exhibits excellent film-forming capacity, film strength, and gelation ability, so as to be used as a material for making hard capsules without the use of coagulants and plasticizers.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Ruei-Jan CHANG, Hsin-Yi CHAO, Pei-Hsuan LEE, Wei-Yu CHEN
  • Vertical interconnect features and methods of forming
    Patent number: 11107896
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE
    Publication number: 20210265202
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • POLISHING INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICES
    Publication number: 20210257248
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Application
    Filed: July 31, 2020
    Publication date: August 19, 2021
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-YI Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu