Patents by Inventor Yi-Che Lai
Yi-Che Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10199341Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.Type: GrantFiled: August 1, 2016Date of Patent: February 5, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
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Patent number: 10062651Abstract: A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to the first region, and a material layer formed on the second region to prevent the substrate body from warping. An electronic package having the packaging substrate is also provided.Type: GrantFiled: March 8, 2016Date of Patent: August 28, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Chang-Fu Lin
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Patent number: 10049975Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.Type: GrantFiled: September 7, 2016Date of Patent: August 14, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
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Patent number: 9899308Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: February 16, 2017Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9875981Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: GrantFiled: October 19, 2016Date of Patent: January 23, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Publication number: 20170317040Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.Type: ApplicationFiled: August 1, 2016Publication date: November 2, 2017Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
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Publication number: 20170311445Abstract: A substrate structure is provided, which includes a substrate having a plurality of conductors and at least a receiving space formed on a surface of the substrate with the receiving space free from penetrating the substrate. During an encapsulating process, an encapsulant can be filled in the receiving space so as to strengthen the bonding between the substrate and the encapsulant, thereby preventing delamination from occurring therebetween.Type: ApplicationFiled: August 3, 2016Publication date: October 26, 2017Inventors: Hung-Hsien Chang, Jyun-Ling Tsai, Yu-Ling Yeh, Wen-Tsung Tseng, Yi-Che Lai
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Patent number: 9754898Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.Type: GrantFiled: June 20, 2013Date of Patent: September 5, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Mu-Hsuan Chan, Wan-Ting Chen, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20170236783Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Publication number: 20170229386Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.Type: ApplicationFiled: September 7, 2016Publication date: August 10, 2017Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
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Publication number: 20170229387Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: ApplicationFiled: February 16, 2017Publication date: August 10, 2017Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9720013Abstract: A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.Type: GrantFiled: October 2, 2013Date of Patent: August 1, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pin-Cheng Huang, Yi-Che Lai
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Publication number: 20170186702Abstract: A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to the first region, and a material layer formed on the second region to prevent the substrate body from warping. An electronic package having the packaging substrate is also provided.Type: ApplicationFiled: March 8, 2016Publication date: June 29, 2017Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Chang-Fu Lin
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Patent number: 9666536Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: GrantFiled: December 2, 2015Date of Patent: May 30, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Publication number: 20170148761Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: January 6, 2017Publication date: May 25, 2017Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
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Patent number: 9627226Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.Type: GrantFiled: March 23, 2016Date of Patent: April 18, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chun-Tang Lin, Yi-Che Lai
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Patent number: 9607974Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: GrantFiled: November 13, 2015Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Patent number: 9607939Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: April 23, 2014Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Publication number: 20170053859Abstract: A method for fabricating an electronic package is provided, including the steps of: providing an interposer having a plurality of conductive vias and at least an opening formed at a periphery of the conductive vias; disposing at least an electronic element on the interposer; and bonding a cover plate to the electronic element and forming an encapsulant between the cover plate and the interposer so as to encapsulate the electronic element and fill the opening, thus allowing the encapsulant in the opening to come into contact with air. As such, during a subsequent high temperature process, evaporated solvents can flow out of the encapsulant through the opening without forming bubbles in the encapsulant, thereby preventing a bubble explosion from occurring. The invention further provides an electronic package.Type: ApplicationFiled: December 29, 2015Publication date: February 23, 2017Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai
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Publication number: 20170040277Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu