Patents by Inventor Yi-Che Lai
Yi-Che Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9548220Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: January 4, 2016Date of Patent: January 17, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 9520304Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.Type: GrantFiled: November 7, 2013Date of Patent: December 13, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 9502333Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: GrantFiled: October 17, 2013Date of Patent: November 22, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Patent number: 9418874Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: GrantFiled: May 19, 2015Date of Patent: August 16, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20160204093Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.Type: ApplicationFiled: March 23, 2016Publication date: July 14, 2016Inventors: Chun-Tang Lin, Yi-Che Lai
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Publication number: 20160190099Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: ApplicationFiled: December 2, 2015Publication date: June 30, 2016Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Patent number: 9349705Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: GrantFiled: February 6, 2015Date of Patent: May 24, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20160141227Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Publication number: 20160118271Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 9324582Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.Type: GrantFiled: June 20, 2013Date of Patent: April 26, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chun-Tang Lin, Yi-Che Lai
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Patent number: 9269693Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.Type: GrantFiled: January 23, 2015Date of Patent: February 23, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
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Patent number: 9257381Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: December 20, 2012Date of Patent: February 9, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20150255311Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: ApplicationFiled: May 19, 2015Publication date: September 10, 2015Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Patent number: 9087780Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.Type: GrantFiled: April 29, 2013Date of Patent: July 21, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wan-Ting Chen, Mu-Hsuan Chan, Yi-Chian Liao, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20150155258Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: ApplicationFiled: February 6, 2015Publication date: June 4, 2015Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20150132893Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
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Patent number: 8987012Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.Type: GrantFiled: March 18, 2013Date of Patent: March 24, 2015Assignee: Siliconwave Precision Industries Co., Ltd.Inventors: Pin-Cheng Huang, Chun-Tang Lin, Wen-Tsung Tseng, Yi-Che Lai
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Publication number: 20150069628Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: ApplicationFiled: April 23, 2014Publication date: March 12, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Publication number: 20150041969Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.Type: ApplicationFiled: November 7, 2013Publication date: February 12, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 8952537Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: GrantFiled: November 15, 2012Date of Patent: February 10, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai