Patents by Inventor Yi-Chen Lo
Yi-Chen Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11289586Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.Type: GrantFiled: August 11, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yi-Chen Lo
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Publication number: 20220052174Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yi-Chen LO
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Publication number: 20220029002Abstract: A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Inventors: Yi-Chen LO, Li-Te LIN, Yu-Lien HUANG
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Publication number: 20220020595Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.Type: ApplicationFiled: January 20, 2021Publication date: January 20, 2022Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
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Patent number: 11217487Abstract: A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.Type: GrantFiled: November 19, 2019Date of Patent: January 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yi-Chen Lo, Li-Te Lin, Pinyen Lin
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Patent number: 11180789Abstract: The present invention provides a method for bioconversion of mogroside extracts into siamenoside I, comprising: using (1) DbExg1 protein or (2) a microorganism expressing the DbExg1 protein to contact or to cultivate with the mogroside extracts. The present invention can convert the mogroside extracts into siamenoside I, which has a higher sweetening power and better taste than other mogrosides. The method of the present invention uses a microorganism expressing the responsible enzyme, DbExg1, which was identified as a mediator of mogroside V conversion into siamenoside I in the present invention, so that siamenoside I was preferentially produced. Thus, the use of the method of the present invention provides a feasible approach to produce large quantities of the natural sweetener, siamenoside I, which can then be applied in several industries.Type: GrantFiled: September 26, 2019Date of Patent: November 23, 2021Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Yi-Chen Lo, Ting-Jang Lu, Reuben Wang
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Patent number: 11145749Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.Type: GrantFiled: December 21, 2018Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Lo, Yu-Lien Huang, Li-Te Lin
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Publication number: 20210210614Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Publication number: 20210095326Abstract: The present invention provides a method for bioconversion of mogroside extracts into siamenoside I, comprising: using (1) DbExg1 protein or (2) a microorganism expressing the DbExg1 protein to contact or to cultivate with the mogroside extracts. The present invention can convert the mogroside extracts into siamenoside I, which has a higher sweetening power and better taste than other mogrosides. The method of the present invention uses a microorganism expressing the responsible enzyme, DbExg1, which was identified as a mediator of mogroside V conversion into siamenoside I in the present invention, so that siamenoside I was preferentially produced. Thus, the use of the method of the present invention provides a feasible approach to produce large quantities of the natural sweetener, siamenoside I, which can then be applied in several industries.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventors: Yi-Chen LO, Ting-Jang LU, Reuben WANG
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Patent number: 10957779Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: GrantFiled: October 11, 2018Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
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Publication number: 20200357899Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
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Patent number: 10741671Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.Type: GrantFiled: September 20, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Lo, Li-Te Lin, Pinyen Lin
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Publication number: 20200176323Abstract: A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.Type: ApplicationFiled: November 19, 2019Publication date: June 4, 2020Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
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Publication number: 20190165123Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: ApplicationFiled: October 11, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Publication number: 20190165132Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.Type: ApplicationFiled: September 20, 2018Publication date: May 30, 2019Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
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Publication number: 20190148524Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.Type: ApplicationFiled: December 21, 2018Publication date: May 16, 2019Inventors: Yi-Chen LO, Yu-Lien HUANG, Li-Te LIN
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Patent number: 10164067Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.Type: GrantFiled: July 7, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chen Lo, Li-Te Lin, Yu-Lien Huang
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Patent number: 10050149Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.Type: GrantFiled: May 18, 2017Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Tsai-Chun Li, Ching-Feng Fu, Ming-Huan Tsai, D. T. Lee, Cheng-Hua Yang, Yi-Chen Lo
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Publication number: 20180175171Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.Type: ApplicationFiled: July 7, 2017Publication date: June 21, 2018Inventors: Yi-Chen LO, Li-Te LIN, Yu-Lien HUANG
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Publication number: 20110012859Abstract: A resistance type touch panel includes a first substrate, a second substrate and a detection module. The first substrate further includes a touch module at a bottom surface thereof facing the second substrate, in which the touch module has a plurality of conductive blocks having individual signal lines. The second substrate includes a bias-layer module at an upper surface thereof opposing to the touch module by a predetermined spacing. The bias-layer module further includes at least four bias points accounted for at least two voltage biases along two directions. The detection module is electrically coupled with the signal lines of the touch module for realizing all the voltage changes among the conductive blocks.Type: ApplicationFiled: December 4, 2009Publication date: January 20, 2011Applicant: ULTRA CHIP INC.Inventors: WEN-KUEI LAI, SHIH-HSIN JUAN, CHENG-HSIN LU, WEI-LUNG HUANG, YI-CHEN LO, CHIH-JUNG CHEN