Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: A driving device for driving a light source module (12) includes an input current limiting circuit (10) and an inverter (11). The input current limiting circuit includes an input current sensing circuit (100) and a feedback compensation circuit (103), for limiting current of an input power signal of the driving device to a predetermined range. The input current sensing circuit is used for sensing a current signal of the input power signal of the driving device. The feedback compensation circuit is connected to the input current sensing circuit, for outputting a compensation signal according to the sensed current signal. The inverter is connected between the input current limiting circuit and the light source module, and includes a feedback circuit (112). The feedback circuit is connected to the feedback compensation circuit, for receiving the compensation signal and feeding back current flowing through the light source module.

Abstract: A driving device for driving a lamp (L) includes a power stage circuit (21), a transformer circuit (22), a voltage dividing circuit (23), an inrush current sensing circuit (24), and a controller circuit (26). The power stage circuit converts a received direct current (DC) signal to an alternating current (AC) signal. The transformer circuit is connected to the power stage circuit, for converting the AC signal to an appropriate signal to drive the lamp. The voltage dividing circuit is connected to the transformer circuit, for dividing voltage of the signal output from the transformer circuit. The inrush current sensing circuit is connected to the voltage dividing circuit, for sensing inrush current output from the transformer circuit. The controller circuit is connected to the power stage circuit, for controlling output of the power stage circuit according to output of the inrush current sensing circuit.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

Abstract: A driving device for driving a light source module (12) includes an input current limiting circuit (10) and an inverter (11). The input current limiting circuit includes an input current sensing circuit (100) and a feedback compensation circuit (103), for limiting current of an input power signal of the driving device to a predetermined range. The input current sensing circuit is used for sensing a current signal of the input power signal of the driving device. The feedback compensation circuit is connected to the input current sensing circuit, for outputting a compensation signal according to the sensed current signal. The inverter is connected between the input current limiting circuit and the light source module, and includes a feedback circuit (112). The feedback circuit is connected to the feedback compensation circuit, for receiving the compensation signal and feeding back current flowing through the light source module.

Abstract: A power supply system for powering backlight lamps in a flat panel display with reduced dimensions and increased power efficiency. The power supply system includes a converter circuit for converting an alternating current (AC) signal from an AC power source to a high direct current (DC) signal, and a high voltage (HV) inverter system that includes a power stage circuit, a transformer circuit, and a current balance circuit. The HV inverter system is coupled to the converter circuit and specifically configured to convert the high DC signal into an AC output signal to power the backlight lamps.

Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract: A loading device for loading a substrate includes: a support module having at least a contact region contacted with the substrate for providing a supporting force to load the substrate; and a conductive media, electrically connected to the contact region and a voltage level, for eliminating electrostatic discharges between the contact region and the substrate.

Abstract: During a communication session (101) for a multi-network user platform (which communication session is presently occurring in a first network and is terminable by a Session Initiation Protocol server as comprises a part of that first network), one establishes (102) in the first network a Session Initiation Protocol instance as corresponds to the communication session. Thereafter, and particularly following a handoff of the communication session from the first network to a second network, one uses (104) the Session Initiation Protocol instance to maintain communications with the Session Initiation Protocol server such that the Session Initiation Protocol server does not terminate the communication session.

Abstract: During (101) a communication session for a plurality of user platforms wherein at least one of the user platforms is on hold and wherein the communication session is presently occurring in a first network and is terminable by a Session Initiation Protocol server as comprises a part of that first network, one establishes (102) in the first network a Session Initiation Protocol instance as corresponds to the communication session wherein the Session Initiation Protocol instance comprises, at least in part, session context information for the user platform that is on hold. Then, following a handoff of bearer support of the communication session from the first network to a second network, one uses (104) the Session Initiation Protocol instance to maintain the hold status of the user platform that is on hold with the Session Initiation Protocol server subsequent to the handoff such that the Session Initiation Protocol server does not terminate the communication session.

Abstract: One detects (101) an indication from an initiator of a presently supported ad-hoc conference call who seeks to transfer chairmanship of the presently supported ad-hoc conference call to another conference call participant. The chairmanship is then transferred (102) to this other participant to thereby provide a presently supported ad-hoc conference call having a transferred chairman.

Abstract: A power supply system for powering backlight lamps in a flat panel display with reduced dimensions and increased power efficiency. The power supply system includes a converter circuit for converting an alternating current (AC) signal from an AC power source to a high direct current (DC) signal, and a high voltage (HV) inverter system that includes a power stage circuit, a transformer circuit, and a current balance circuit. The HV inverter system is coupled to the converter circuit and specifically configured to convert the high DC signal into an AC output signal to power the backlight lamps.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

Abstract: A process scheduling system and method. The system includes a fetch module, a timing scheduling module and a trigger module. The fetch module fetches resource status data of at least one resource item of an application system periodically. The timing scheduling module dynamically determines an execution time point for at least one process according to the resource status data. The trigger module executes the process at the execution time point. The fetch module further fetches the resource status data as feedback for further determination after the process is executed.

Abstract: This invention teaches a computerized method for use in data acquisition and manipulation of two-dimensional patterns in the fields of medicine, astronomy, chemistry, biology and biotechnology. The invention teaches an interactive computerized method for matching visual patterns of polypeptide spots in two-dimensional (2-D) gel electrophoretogram solubilized into polypeptide constituents that are separated by electrophoresis. The computerized method manipulates spot pixel coordinates using staged coordinate transformation techniques on spot markers and unknown study spots to reduce gel preparation distortions and allows a user to produce matching results in a manner that compares the transformed spot data using either a single reference gel or multiple reference gels approach for producing the matching results. The method also includes a spot matching verification step and a step to extract potentially mis-matched spots from reported matching results.