Patents by Inventor Yi-Cheng Tsai

Yi-Cheng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240246183
    Abstract: A modular machine tool processing jig includes a base body having at least a positioning device and a movement adjusting device; at least a clamping positioning seat fixed on the base body through the positioning device and having at least a positioning clamping face, by which providing an efficient and accurate positioning effect; and at least a clamping adjusting seat disposed on the base body through the movement adjusting device, so as to adjust the interval between the clamping adjusting seat and the clamping positioning seat along an axial direction for different workpiece sizes. Therein, the clamping adjusting seat has at least a clamping assembly having at least a clamping face. The clamping assembly adjusts the interval between the clamping face and the positioning clamping face for clamping a to-be-processed workpiece.
    Type: Application
    Filed: May 2, 2023
    Publication date: July 25, 2024
    Inventor: YI-CHENG TSAI
  • Patent number: 12032505
    Abstract: A command transforming method, applied to a command transforming system comprising a first transceiving interface and a second transceiving interface, comprising: receiving at least one command transmitted from a first device via the first transceiving interface; determining a first sequence rule of the first device and a second sequence rule of a second device, wherein the first sequence rule means if the first device is required to process the command in sequence and the second sequence rule means if the second device is required to process the command in sequence; transmitting the command to the second device via the second transceiving interface; processing the command by the second device according to the second sequence rule and transmitting a response corresponding to the command to the second transceiving interface by the second device; and transmitting the response to the first device according to the first sequence rule.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: July 9, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Cheng Tsai, Chi-Rung Wu
  • Publication number: 20240126633
    Abstract: A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 18, 2024
    Inventors: Yi Cheng TSAI, Sung-Kao LIU, Cheng-Yuan HSIAO, Po-Hao CHEN
  • Publication number: 20240071225
    Abstract: A risk control system for traffic devices includes a light emitting device, a processing element and a user prompting element. The processing element is electrically connected with the light emitting device, and outputs a prompt signal. The user prompting element is electrically connected with the processing element, and receives the prompt signal.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Inventors: Yu-Chien KAO, Chueh-Yuan NIEN, Yi-Cheng TSAI
  • Patent number: 11749225
    Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: September 5, 2023
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventor: Yi-Cheng Tsai
  • Publication number: 20230153262
    Abstract: A command transforming method, applied to a command transforming system comprising a first transceiving interface and a second transceiving interface, comprising: receiving at least one command transmitted from a first device via the first transceiving interface; determining a first sequence rule of the first device and a second sequence rule of a second device, wherein the first sequence rule means if the first device is required to process the command in sequence and the second sequence rule means if the second device is required to process the command in sequence; transmitting the command to the second device via the second transceiving interface; processing the command by the second device according to the second sequence rule and transmitting a response corresponding to the command to the second transceiving interface by the second device; and transmitting the response to the first device according to the first sequence rule.
    Type: Application
    Filed: February 23, 2022
    Publication date: May 18, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Cheng Tsai, Chi-Rung Wu
  • Publication number: 20230154430
    Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.
    Type: Application
    Filed: October 24, 2022
    Publication date: May 18, 2023
    Inventor: Yi-Cheng TSAI
  • Patent number: 10833197
    Abstract: The TFT substrate has a plurality of pixels and a plurality of TFTs (10). The TFT substrate includes a first conductive layer (12) including a gate electrode (12g) of the TFT, a gate insulating layer (13), a semiconductor layer (14), a protective insulating layer (15) including a portion covering a channel region (14c) and having a first opening portion (15a) reaching the drain electrode (14s) and a second opening portion (15b) reaching the drain region (14d), and a second conductive layer (16) including a source electrode (16s) and a drain electrode (16d). Each of the plurality of pixels has a compensation capacitance unit (30), the first conductive layer further includes a first electrode unit (12a) electrically connected to the gate electrode and forming a compensation capacitance unit, and the second conductive layer further includes a second electrode unit (16a) electrically connected to the drain electrode, overlapping the first electrode unit, and forming a compensation capacitance unit.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: November 10, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yi-Cheng Tsai
  • Patent number: 10546537
    Abstract: A display device includes a display panel and display drivers disposed on the display panel. The distance between a first display driver and a second display driver of the display drivers is greater than the distance between a second display driver and a third display driver of the display drivers. The display panel includes a curved segment adjacent to an area between the first display driver and the second display driver.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: January 28, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Cheng Tsai, Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung
  • Patent number: 10529296
    Abstract: To a unit circuit, provided are a transistor to which a first clock signal is supplied, a transistor for applying an off-level voltage to a first node, a transistor for applying the off-level voltage to a second node, a transistor for applying an on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a forward direction scanning, a transistor for applying the on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a backward direction scanning, and a circuit for controlling a voltage of the first node based on output signals of the unit circuits in a front-side stage and a back-side stage. The unit circuit is configured so that a voltage of the second node is changed to an ON level and an OFF level while a voltage of the first node is in the OFF level and the voltage of the second node is in the ON level when the first clock signal is changed to the ON level while the voltage of the first node is in the OFF level.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yi-Cheng Tsai, Satoshi Horiuchi
  • Publication number: 20190245095
    Abstract: The TFT substrate has a plurality of pixels and a plurality of TFTs (10). The TFT substrate includes a first conductive layer (12) including a gate electrode (12g) of the TFT, a gate insulating layer (13), a semiconductor layer (14), a protective insulating layer (15) including a portion covering a channel region (14c) and having a first opening portion (15a) reaching the drain electrode (14s) and a second opening portion (15b) reaching the drain region (14d), and a second conductive layer (16) including a source electrode (16s) and a drain electrode (16d). Each of the plurality of pixels has a compensation capacitance unit (30), the first conductive layer further includes a first electrode unit (12a) electrically connected to the gate electrode and forming a compensation capacitance unit, and the second conductive layer further includes a second electrode unit (16a) electrically connected to the drain electrode, overlapping the first electrode unit, and forming a compensation capacitance unit.
    Type: Application
    Filed: October 13, 2017
    Publication date: August 8, 2019
    Inventor: Yi-Cheng TSAI
  • Publication number: 20190147820
    Abstract: To a unit circuit, provided are a transistor to which a first clock signal is supplied, a transistor for applying an off-level voltage to a first node, a transistor for applying the off-level voltage to a second node, a transistor for applying an on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a forward direction scanning, a transistor for applying the on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a backward direction scanning, and a circuit for controlling a voltage of the first node based on output signals of the unit circuits in a front-side stage and a back-side stage. The unit circuit is configured so that a voltage of the second node is changed to an ON level and an OFF level while a voltage of the first node is in the OFF level and the voltage of the second node is in the ON level when the first clock signal is changed to the ON level while the voltage of the first node is in the OFF level.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Inventors: YI-CHENG TSAI, SATOSHI HORIUCHI
  • Publication number: 20180122303
    Abstract: A display device includes a display panel and display drivers disposed on the display panel. The distance between a first display driver and a second display driver of the display drivers is greater than the distance between a second display driver and a third display driver of the display drivers. The display panel includes a curved segment adjacent to an area between the first display driver and the second display driver.
    Type: Application
    Filed: October 17, 2017
    Publication date: May 3, 2018
    Inventors: Yi-Cheng TSAI, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG
  • Publication number: 20160146920
    Abstract: An RF parameter calibration method comprises steps: measuring an open-circuit parameter, a short-circuit parameter and a load parameter of an RF parameter circuit of a tested object; respectively substituting measured values of the open-circuit parameter, the short-circuit parameter and the load parameter into a directivity error equation, a signal source matching error equation, and a reflection path error equation to obtain a directivity error, a signal source matching error, and a reflection path error; substituting the directivity error, the signal source matching error and the reflection path error into an RF parameter equation to work out an actual value of an RF parameter; examining whether the actual value of the RF parameter is smaller than a preset dB value; if yes, undertaking calibration; if no, returning to undertake measurements once again. The present invention can replace the expensive standard calibration kit and achieve more precise parameter calibration.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Inventors: CHIEN-HUNG LIN, YI-CHENG TSAI, CHING-CHENG TIEN, CHI-CHUNG LIU
  • Patent number: 9281356
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Publication number: 20150205413
    Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.
    Type: Application
    Filed: March 30, 2015
    Publication date: July 23, 2015
    Inventors: Guang-Yi ZENG, Liang-Hao KANG, Yi-Cheng TSAI
  • Patent number: 9018535
    Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Guang-Yi Zeng, Liang-Hao Kang, Yi-Cheng Tsai
  • Publication number: 20150111361
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 8921946
    Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 8836633
    Abstract: In a display driving circuit, odd-stage shift registers (SRs) are cascaded; and even-stage SRs are cascaded. The SRs support dual direction shifting. Each SR includes: first, second, third, and fourth transistors. The first transistor is coupled to a forward scan start signal from a third transistor of a former second SR, coupled to an output signal from the former second SR and coupled to a node. The second transistor is coupled to a reverse scan start signal from a fourth transistor of a next second SR, coupled to an output signal from the next second SR and coupled to the node. The third transistor is coupled to a forward operation voltage and coupled to the node, and further outputs a forward scan start signal. The fourth transistor is coupled to a reverse operation voltage and coupled to the node, and further outputs a reverse scan start signal.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 16, 2014
    Assignee: Innolux Corporation
    Inventors: Yi-Cheng Tsai, Hung-Chih Sun, Gau-Bin Chang, Yi-Yuan Lin