Abstract: An electronic device including a plurality of pixels and a driving element is provided. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The driving element drives each first sub-pixel of the plurality of pixels.

Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

Abstract: An electronic device includes a substrate, a driving element, a first transparent conductive layer, an insulating layer, and a second transparent conductive layer. The driving element is disposed on the substrate and includes a drain electrode having a first edge. The first transparent conductive layer is disposed on the driving element. The insulating layer is disposed between the driving element and the first transparent conductive layer and includes a hole through which the first transparent conductive layer is electrically connected to the driving element. The second transparent conductive layer is disposed on the insulating layer. One of the first and second transparent conductive layers includes at least one slit, and the first or second transparent conductive layer that includes the at least one slit has a second edge. The second edge is located in the hole, and the at least one slit exposes the first edge of the drain electrode.

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

Abstract: The art for the design of a class of modified catalysts, the process for preparing such modified catalysts and implementation of such modified catalysts in phosphoric acid fuel cells is disclosed. The modified catalyst comprises a particle of a metal-doped porous material and an amount of a phosphate-containing acid group or phosphate-containing acid groups. The particle of the metal-doped porous material is a particle of a porous carrier with metal microparticles and a plurality of hydroxyl groups on the surface of the porous carrier such that (i) the plurality of metal microparticles are attached to a first portion of the plurality of hydroxyl groups of the surface of the porous carrier and (ii) an amount of a phosphate-containing acid group or phosphate-containing acid groups can be bonded to a second portion of the plurality of hydroxyl groups of the surface of the porous carrier to form the modified catalyst.

Abstract: An electronic device has a plurality of sub-pixels. The electronic device includes a substrate, a gate line and a spacer. The gate line is disposed on the substrate and extends along a first direction. The spacer is disposed on the gate line and overlaps with the gate line. The spacer has a first width W1 along the first direction. One of the plurality of sub-pixels has a sub-pixel pitch P along the first direction. The first width W1 and the sub-pixel pitch P satisfy the following relationship: P?W1.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: A method for preventing a robot from colliding with another robot that is provided with an identifying image includes steps of: controlling the robot to move along a predetermined path; stopping the robot when it is determined that a first image captured by the robot while the robot is moving contains the identifying image; and controlling the robot to resume moving along the predetermined path when it is determined that a second image captured by the robot while the robot is not moving does not contain the identifying image.

Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.

Abstract: An optical system is provided and it includes a first optical module and a second optical module. The first optical module includes a first connecting member for connecting a first optical element. The second optical module includes a second connecting member for connecting a second optical element. The first optical module and the second optical module are arranged in a first direction.

Abstract: In one example in accordance with the disclosure, a computing device is described. An example computing device includes a gaze tracking device. An example gaze tracking device identifies, from a captured image, a gaze region for a user viewing a display device coupled to the example computing device. The gaze region indicates a location on the display device where the user is looking. The example computing device includes a controller. An example controller determines a first window on the display device that is aligned with the gaze region and based on a determination that the first window is aligned with the gaze region, adjusts a video setting of a second window that is outside the gaze region.

Abstract: The present invention provides a pharmaceutical composition for treating chronic stroke, involving injection via brain into the cranium of a patient having chronic stroke for six months or more; the pharmaceutical composition is a suspension at least comprising TS stem cells, an active synergistic component and a growth factor, wherein the expression level of CD34 and CD45 of the TS stem cells is 10% or less, and the expression level of CD90 and CD105 is 90% or more; the active synergistic component is an extracellular vesicle; the growth factor is at least one selected from the group consisting of HGF, G-CSF, Fractalkine, IP-10, EGF, IL-1?, IL-1?, IL-4, IL-5, IL-13, IFN?, TGF? and sCD40L. The present invention overcomes the limitations of previous cell therapy and provides a cell-based preparation that is clinically safe and therapeutically effective for chronic cerebral stroke.

Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.

Abstract: A salt of a neuroceutical and of an acid, wherein the neuroceutical is a substituted benzodiazepine, a substituted benzothiazepine, a substituted pyridopyrimidines or a substituted amino-cyclohexaneacetic acid; and the acid is benzoic acid, nicotinic acid, pantothenic acid and tannic acid. The molar ratio of the neuroceutical and the acid in the salt ranges from about 6:1 to about 1:5. Also disclosed herein are compositions comprising the neuroceutical salt and therapeutic uses thereof for treating a central nervous system (CNS) disorder or a metabolic disorder associated with the CNS disorder.

Abstract: A display device having a first region, a second region, and a third region set between the first region and the second region is provided. The display device includes a first sub-pixel, a second sub-pixel, and a first signal line. The first sub-pixel is arranged in the first region. The second sub-pixel is arranged in the second region, the area of the first sub-pixel is larger than the area of the second sub-pixel. The first signal line is arranged in the first region and the third region, and is electrically connected to the first sub-pixel and the second sub-pixel. At least a part of the first signal line extends in the first direction in the first region. At least another part of the first signal line extends in the second direction in the third region. The first direction is different from the second direction.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.