Abstract: The TFT substrate has a plurality of pixels and a plurality of TFTs (10). The TFT substrate includes a first conductive layer (12) including a gate electrode (12g) of the TFT, a gate insulating layer (13), a semiconductor layer (14), a protective insulating layer (15) including a portion covering a channel region (14c) and having a first opening portion (15a) reaching the drain electrode (14s) and a second opening portion (15b) reaching the drain region (14d), and a second conductive layer (16) including a source electrode (16s) and a drain electrode (16d). Each of the plurality of pixels has a compensation capacitance unit (30), the first conductive layer further includes a first electrode unit (12a) electrically connected to the gate electrode and forming a compensation capacitance unit, and the second conductive layer further includes a second electrode unit (16a) electrically connected to the drain electrode, overlapping the first electrode unit, and forming a compensation capacitance unit.

Abstract: To a unit circuit, provided are a transistor to which a first clock signal is supplied, a transistor for applying an off-level voltage to a first node, a transistor for applying the off-level voltage to a second node, a transistor for applying an on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a forward direction scanning, a transistor for applying the on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a backward direction scanning, and a circuit for controlling a voltage of the first node based on output signals of the unit circuits in a front-side stage and a back-side stage. The unit circuit is configured so that a voltage of the second node is changed to an ON level and an OFF level while a voltage of the first node is in the OFF level and the voltage of the second node is in the ON level when the first clock signal is changed to the ON level while the voltage of the first node is in the OFF level.

Abstract: A display device includes a display panel and display drivers disposed on the display panel. The distance between a first display driver and a second display driver of the display drivers is greater than the distance between a second display driver and a third display driver of the display drivers. The display panel includes a curved segment adjacent to an area between the first display driver and the second display driver.

Abstract: An RF parameter calibration method comprises steps: measuring an open-circuit parameter, a short-circuit parameter and a load parameter of an RF parameter circuit of a tested object; respectively substituting measured values of the open-circuit parameter, the short-circuit parameter and the load parameter into a directivity error equation, a signal source matching error equation, and a reflection path error equation to obtain a directivity error, a signal source matching error, and a reflection path error; substituting the directivity error, the signal source matching error and the reflection path error into an RF parameter equation to work out an actual value of an RF parameter; examining whether the actual value of the RF parameter is smaller than a preset dB value; if yes, undertaking calibration; if no, returning to undertake measurements once again. The present invention can replace the expensive standard calibration kit and achieve more precise parameter calibration.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.

Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: In a display driving circuit, odd-stage shift registers (SRs) are cascaded; and even-stage SRs are cascaded. The SRs support dual direction shifting. Each SR includes: first, second, third, and fourth transistors. The first transistor is coupled to a forward scan start signal from a third transistor of a former second SR, coupled to an output signal from the former second SR and coupled to a node. The second transistor is coupled to a reverse scan start signal from a fourth transistor of a next second SR, coupled to an output signal from the next second SR and coupled to the node. The third transistor is coupled to a forward operation voltage and coupled to the node, and further outputs a forward scan start signal. The fourth transistor is coupled to a reverse operation voltage and coupled to the node, and further outputs a reverse scan start signal.

Abstract: A pixel array substrate includes a substrate, a plurality of pixel structures, a plurality of signal lines, a plurality of first traces, a plurality of second traces, a plurality of first conductive structures, and a plurality of second conductive structures. The pixel structures are arranged in array in a display region of the substrate. The signal lines are disposed in the display region and are formed in a first conducting wire layer and are electrically connected to the pixel structures. The first traces and the second traces are disposed in a periphery circuit region of the substrate and are respectively formed in a second conducting wire layer and the first conducting wire layer. A part of the signal lines are electrically connected to the first traces by the first conductive structures. Another of the signal lines are electrically connected to the second traces by the second conductive structures.

Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.

Abstract: A wiring structure of a liquid crystal display (LCD) panel is provided. The wiring structure includes: a gate electrode layer, formed on a glass substrate; a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is defined on the gate electrode layer; a source/drain electrode layer, formed on the first insulating layer, in which the source/drain electrode layer and the gate electrode layer are horizontally staggered; a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and an indium tin oxide (ITO) layer, formed on the first opening, the second opening, and/or the second insulating layer. Thus, the high impedance of the ITO layer for connecting the gate electrode layer with the source/drain electrode layer is reduced.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: A driving method for driving a display apparatus is provided. The driving method includes: configuring a plurality of driving voltages corresponding to a plurality of gray scales, where the gray scales include a first gray scale and a second gray scale smaller than the first gray scale, and a first driving voltage corresponding to the first gray scale is lower than a second driving voltage corresponding to the second gray scale; and controlling the display apparatus to display a gray scale merely up to the second gray scale. In this way, the driving method hence reduces the response time of the display apparatus, which may be an LCD display panel.

Abstract: A pixel array substrate includes a substrate, a plurality of pixel structures, a plurality of signal lines, a plurality of first traces, a plurality of second traces, a plurality of first conductive structures, and a plurality of second conductive structures. The pixel structures are arranged in array in a display region of the substrate. The signal lines are disposed in the display region and are formed in a first conducting wire layer and are electrically connected to the pixel structures. The first traces and the second traces are disposed in a periphery circuit region of the substrate and are respectively formed in a second conducting wire layer and the first conducting wire layer. A part of the signal lines are electrically connected to the first traces by the first conductive structures. Another of the signal lines are electrically connected to the second traces by the second conductive structures.

Abstract: A substrate module suitable for being filled with a display medium to form a display panel is provided. The substrate module includes an active device array substrate, an opposite substrate, and a sealant. The active device array substrate has a groove. The opposite substrate is disposed opposite to the active device array substrate. The active device array substrate and the opposite substrate are assembled through the sealant, wherein the display medium is substantially filled in a region surrounded by the sealant to form the display panel and the groove is located between the sealant and a border of the active device array substrate.

Abstract: A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.

Abstract: A flat panel display including a glass substrate, a source driving unit and a gate driving unit is provided. An nth shift register of the gate driving unit includes a pull-up unit, a driving unit, a pull-down unit and a driving control unit. When the driving unit turns on the pull-up unit according to a trigger signal and the pull-up unit enables an output terminal to output an nth output signal according to a first clock signal, the driving control unit turns off the pull-down unit. The trigger signal is an (n?1)th output signal or a start signal. Afterwards, the driving control unit provides a DC level voltage according to a second clock signal to drive the pull-down unit, and the pull-down unit enables the output terminal to output a low level voltage. The DC level voltage is between a high level voltage of the nth output signal and the low level voltage.

Abstract: A transistor array substrate includes a substrate, plural pads, plural shorting bars, at least one pixel array, plural first wires, and plural second wires. The substrate has at least one panel region and a peripheral circuit region surrounding the panel region. The pads and the shorting bars are disposed in the peripheral circuit region. The pixel array, the first wires, and the second wires are disposed in the panel region. The panel region has a pair of first edges and a pair of second edges. The first edges are connected between the second edges. The shorting bars are connected to the pads. The first wires and the second wires are electrically connected to the pixel array. The first wires are connected to some shorting bars through one of the first edges. The second wires are connected to the other shorting bars through at least one second edge.