Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element stacking structure is disposed on a carrier structure to integrate multiple chips into a single package, so that the electronic package can meet with the requirements of miniaturization without increasing the layout area of the carrier structure.

Abstract: An electronic package and the manufacturing method thereof are provided, in which a first electronic element and a second electronic element are disposed on a carrier structure, and the first electronic element and the second electronic element are electrically connected to each other by a wire. Therefore, by replacing some layers of the circuit layer of the carrier structure with the wire, the carrier structure can satisfy the functional signal transmission of the first and second electronic elements without configuring too many circuit layers, so as to shorten the process steps and time of the carrier structure, thereby effectively reducing the manufacturing cost of the electronic package.

Abstract: An electronic device, a carrying buckle, and a carrying frame of a carrying buckle are provided. The carrying frame is integrally formed as a single one-piece structure and is insertable into a retaining case along an insertion direction for being fixed in the retaining case. The carrying frame includes a body segment, two buckling arms respectively extending from two opposite sides of the body segment, and an elastic structure that extends from the body segment. The elastic structure is elastically deformable when being pressed along the insertion direction, such that an abutting end of each of the two buckling arms has a displacement that allows the abutting end to be abutted against the retaining case.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A connector combination structure is provided. The connector combination structure includes a first connector and a second connector. The first connector includes a first joint and at least one wedging portion. The second connector includes a housing, a second joint and at least one wedging arm. The second joint and the wedging arm are disposed in the housing. The wedging arm is adapted to be rotated between a first arm position and a second arm position. The first joint is adapted to be inserted into the housing to be connected to the second joint. When the wedging arm is located in the first arm position, the wedging arm is adapted to wedge the wedging portion. When the wedging arm is in the second arm position, the wedging arm is adapted to release the wedging portion.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A connector combination structure is provided. The connector combination structure includes a first connector and a second connector. The first connector includes a first joint and at least one wedging portion. The second connector includes a housing, a second joint and at least one wedging arm. The second joint and the wedging arm are disposed in the housing. The wedging arm is adapted to be rotated between a first arm position and a second arm position. The first joint is adapted to be inserted into the housing to be connected to the second joint. When the wedging arm is located in the first arm position, the wedging arm is adapted to wedge the wedging portion. When the wedging arm is in the second arm position, the wedging arm is adapted to release the wedging portion.

Abstract: A cathode assembly for a physical vapor deposition (PVD) system includes a target holder and a thickness detector. The target holder is for holding a target, in which the target has a first major surface and a second major surface. The first major surface and the second major surface are respectively proximal and distal to the target holder. The thickness detector is disposed on the target holder. At least one portion of the first major surface is exposed to the thickness detector for allowing the thickness detector to detect the thickness of the target through the first major surface.

Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Abstract: A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Abstract: A cathode assembly for a physical vapor deposition (PVD) system includes a target holder and a thickness detector. The target holder is for holding a target, in which the target has a first major surface and a second major surface. The first major surface and the second major surface are respectively proximal and distal to the target holder. The thickness detector is disposed on the target holder. At least one portion of the first major surface is exposed to the thickness detector for allowing the thickness detector to detect the thickness of the target through the first major surface.

Abstract: A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Abstract: The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.

Abstract: A decoupling circuit for enhancing isolation of two monopole antennas is disclosed. The two monopole antennas substantially symmetrically stand on a bottom, and a gap is formed between the two monopole antennas. The decoupling circuit includes a grounding element located on the bottom and electrically connected to a ground, a connection bar substantially perpendicular to the bottom, including a first terminal electrically connected to the grounding element, a second terminal extending to the gap, a first branch extending from the second terminal of the connection bar to a first monopole antenna of the two monopole antennas, and a second branch extending from the second terminal of the connection bar to a second monopole antenna of the two monopole antennas.