Patents by Inventor Yi-Ching Wu

Yi-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11287898
    Abstract: A backlight module includes a light-shielding sheet, a light guide plate under the light-shielding sheet, a reflective sheet under the light guide plate, a main circuit board under the reflective sheet, a light-emitting unit on the main circuit board, a flexible circuit board under the reflective sheet, and an electrical connector electrically connected to the flexible circuit board and the main circuit board. A protrusion of the reflective sheet protrudes into a through hole of the light guide plate. The light-emitting unit passes through an opening of the reflective sheet to be accommodated in a slot hole of the light guide plate. The light-emitting unit is configured to emit light to reach a light exit area of the light-shielding sheet through the light guide plate. The electrical connector is aligned with the through hole or further protrudes into the through hole.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 29, 2022
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Hsuan-Wei Ho, Yi-Ching Wu
  • Publication number: 20220026994
    Abstract: A backlight module includes a light-shielding sheet, a light guide plate under the light-shielding sheet, a reflective sheet under the light guide plate, a main circuit board under the reflective sheet, a light-emitting unit on the main circuit board, a flexible circuit board under the reflective sheet, and an electrical connector electrically connected to the flexible circuit board and the main circuit board. A protrusion of the reflective sheet protrudes into a through hole of the light guide plate. The light-emitting unit passes through an opening of the reflective sheet to be accommodated in a slot hole of the light guide plate. The light-emitting unit is configured to emit light to reach a light exit area of the light-shielding sheet through the light guide plate. The electrical connector is aligned with the through hole or further protrudes into the through hole.
    Type: Application
    Filed: December 3, 2020
    Publication date: January 27, 2022
    Inventors: Hsuan-Wei HO, Yi-Ching WU
  • Patent number: 11171608
    Abstract: The present invention is to provide a mixing circuit, comprising: a first transistor; a second transistor; a third transistor; a first connection point connected to a gate terminal of the first transistor, a drain terminal of the second transistor and a source terminal of the third transistor; a second connection point connected to a source terminal of the first transistor and a gate terminal of the second transistor; and a third connection point connected to a drain terminal of the first transistor and a drain terminal of the third transistor.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 9, 2021
    Assignee: ACADEMIA SINICA
    Inventors: Yi-Ching Wu, Yuh-Jing Hwang, Chau-Ching Chiong, Bo-Ze Lu, Huei Wang
  • Publication number: 20210320623
    Abstract: The present invention is to provide a mixing circuit, comprising: a first transistor; a second transistor; a third transistor; a first connection point connected to a gate terminal of the first transistor, a drain terminal of the second transistor and a source terminal of the third transistor; a second connection point connected to a source terminal of the first transistor and a gate terminal of the second transistor; and a third connection point connected to a drain terminal of the first transistor and a drain terminal of the third transistor.
    Type: Application
    Filed: December 6, 2019
    Publication date: October 14, 2021
    Inventors: YI-CHING WU, YUH-JING HWANG, Chau-Ching Chiong, Bo-Ze Lu, HUEI WANG
  • Publication number: 20160329504
    Abstract: Aromatic derivatives having an electron donating group and an electron accepting group at each end are provided. The aromatic derivatives of the present invention can emit blue or green light and may function as a host material or a dopant material. An OLED device using the aromatic derivatives is also herein disclosed.
    Type: Application
    Filed: September 10, 2015
    Publication date: November 10, 2016
    Inventors: Chien-Hong CHENG, Chih-Chun LIN, Yi-Ching WU
  • Patent number: 9378968
    Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Ching Wu, Horng-Bor Lu, Yung-Chieh Kuo
  • Publication number: 20160064241
    Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 3, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YI-CHING WU, HORNG-BOR LU, YUNG-CHIEH KUO
  • Patent number: 9064814
    Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 23, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 9040315
    Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Ching Wu, Tzu-Hung Yang, Chih-Chung Wu
  • Patent number: 8921947
    Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Ching Wu
  • Publication number: 20140374805
    Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
  • Publication number: 20140377887
    Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Yi-Ching WU, Tzu-Hung Yang, Chih-Chung Wu
  • Publication number: 20140361381
    Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Ching Wu
  • Patent number: 8755646
    Abstract: A method of fabricating an optical transformer is provided. A substrate is provided first, wherein the substrate includes a first region and a second region. Then a first material layer is formed on the substrate, and the portion of the first material layer other than in the first region is removed. Then a second material layer is formed on the substrate, and the portion of the second material layer in the first region and the second region is removed. Lastly, a first conductive layer is formed on the substrate and the portion of the first conductive layer other than in the second region is removed to make the first material layer, the second material layer and the first conductive layer have the same height such that the first material layer becomes a part of the optical transformer. The present invention further provides a semiconductor structure.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: June 17, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Ching Wu, Shuenn-Jeng Chen
  • Publication number: 20140159138
    Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: SPANSION LLC
    Inventors: YouSeok SUH, Sung-Yong CHUNG, Ya-Fen LIN, Yi-Ching WU
  • Patent number: 8692310
    Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 8, 2014
    Assignee: Spansion LLC
    Inventors: YouSeok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Wu
  • Publication number: 20130308899
    Abstract: A method of fabricating an optical transformer is provided. A substrate is provided first, wherein the substrate includes a first region and a second region. Then a first material layer is formed on the substrate, and the portion of the first material layer other than in the first region is removed. Then a second material layer is formed on the substrate, and the portion of the second material layer in the first region and the second region is removed. Lastly, a first conductive layer is formed on the substrate and the portion of the first conductive layer other than in the second region is removed to make the first material layer, the second material layer and the first conductive layer have the same height such that the first material layer becomes a part of the optical transformer. The present invention further provides a semiconductor structure.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 21, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ching Wu, Shuenn-Jeng Chen
  • Publication number: 20130282962
    Abstract: A storage control system and method of operation thereof includes: a memory circuit for accessing a configuration category; a configuration module, coupled to the memory circuit, for configuring the memory circuit with the configuration category; and an operation module, coupled to the configuration module, for controlling a performance characteristic of a memory device based on the configuration category.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 24, 2013
    Applicant: SMART Storage Systems, Inc.
    Inventors: Bernardo Rub, James Fitzpatrick, Sheunghee Park, Yi-Ching Wu, Robert W. Ellis
  • Patent number: 8536038
    Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
  • Patent number: 8520987
    Abstract: A method of fabricating an optical transformer is provided. A substrate is provided first, wherein the substrate includes a first region and a second region. Then a first material layer is formed on the substrate, and the portion of the first material layer other than in the first region is removed. Then a second material layer is formed on the substrate, and the portion of the second material layer in the first region and the second region is removed. Lastly, a first conductive layer is formed on the substrate and the portion of the first conductive layer other than in the second region is removed to make the first material layer, the second material layer and the first conductive layer have the same height such that the first material layer becomes a part of the optical transformer.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: August 27, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Ching Wu, Shuenn-Jeng Chen