Patents by Inventor Yi-Ching Wu
Yi-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250141422Abstract: A balun includes a first coil, a second coil, a third coil, a fourth coil, and a capacitor. The first coil is coupled between an unbalanced pin and a first ground terminal. The second coil is coupled between the first ground terminal and a second ground terminal. The third coil is coupled between a first balanced pin and a connection point and is inductively coupled to the first coil. The fourth coil is coupled between the connection point and a second balanced pin and is inductively coupled to the second coil. The capacitor is coupled between the connection point and a third ground terminal.Type: ApplicationFiled: June 4, 2024Publication date: May 1, 2025Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Yi-Ching Wu, Chia-Jun Chang
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Publication number: 20240421791Abstract: The present invention provides a filter configured to receive an input signal to generate a filtered signal. The filter includes a first component, a first capacitor and a second component. The first component is coupled between the input signal and a first terminal. The first capacitor is coupled between the first terminal and a second terminal. For the second component, a first node of the second component is coupled to the second terminal, and a second node of the second component is used to output the filtered signal. The first component and the second component are inductive components.Type: ApplicationFiled: April 14, 2024Publication date: December 19, 2024Applicant: Realtek Semiconductor Corp.Inventors: Yi-Ching Wu, Chia-Jun Chang
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Publication number: 20240178818Abstract: A resistive attenuator and a method for improving linearity of the resistive attenuator are provided. The resistive attenuator includes a first transistor, an attenuation circuit and a compensation circuit, wherein both the first transistor and the attenuation circuit are coupled between an input terminal and an output terminal of the resistive attenuator, and the compensation circuit is coupled to the first transistor. The first transistor is configured to provide a first signal path between the input terminal and the output terminal. The attenuation circuit is configured to provide a second signal path between the input terminal and the output terminal, wherein signal attenuation of the second signal path is greater than signal attenuation of the first signal path. The compensation circuit is configured to compensate nonlinear distortion caused by the first transistor.Type: ApplicationFiled: August 4, 2023Publication date: May 30, 2024Applicant: Realtek Semiconductor Corp.Inventors: Yi-Ching Wu, Chia-Jun Chang
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Publication number: 20240146287Abstract: A frequency mixing circuit includes: a first transistor and a second transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal of the first transistor is configured to receive an oscillation signal, the first terminal of the first transistor is configured to output a mixed signal, and the second terminal of the first transistor is configured to receive a source signal. The second transistor has a control terminal, a first terminal and a second terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor, the first terminal of the second transistor is coupled to the first terminal of the first transistor, and the second terminal of the second transistor is coupled to the control terminal of the first transistor.Type: ApplicationFiled: September 6, 2023Publication date: May 2, 2024Applicant: Realtek Semiconductor Corp.Inventors: Yi-Ching Wu, Chia-Jun Chang
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Patent number: 11588612Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.Type: GrantFiled: October 20, 2021Date of Patent: February 21, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Jon-Jin Chen, Chia-Jun Chang, Ka-Un Chan, Yi-Ching Wu
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Publication number: 20220255717Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.Type: ApplicationFiled: October 20, 2021Publication date: August 11, 2022Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Jon-Jin Chen, Chia-Jun Chang, Ka-Un Chan, Yi-Ching Wu
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Patent number: 11287898Abstract: A backlight module includes a light-shielding sheet, a light guide plate under the light-shielding sheet, a reflective sheet under the light guide plate, a main circuit board under the reflective sheet, a light-emitting unit on the main circuit board, a flexible circuit board under the reflective sheet, and an electrical connector electrically connected to the flexible circuit board and the main circuit board. A protrusion of the reflective sheet protrudes into a through hole of the light guide plate. The light-emitting unit passes through an opening of the reflective sheet to be accommodated in a slot hole of the light guide plate. The light-emitting unit is configured to emit light to reach a light exit area of the light-shielding sheet through the light guide plate. The electrical connector is aligned with the through hole or further protrudes into the through hole.Type: GrantFiled: December 3, 2020Date of Patent: March 29, 2022Assignee: Chicony Power Technology Co., Ltd.Inventors: Hsuan-Wei Ho, Yi-Ching Wu
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Publication number: 20220026994Abstract: A backlight module includes a light-shielding sheet, a light guide plate under the light-shielding sheet, a reflective sheet under the light guide plate, a main circuit board under the reflective sheet, a light-emitting unit on the main circuit board, a flexible circuit board under the reflective sheet, and an electrical connector electrically connected to the flexible circuit board and the main circuit board. A protrusion of the reflective sheet protrudes into a through hole of the light guide plate. The light-emitting unit passes through an opening of the reflective sheet to be accommodated in a slot hole of the light guide plate. The light-emitting unit is configured to emit light to reach a light exit area of the light-shielding sheet through the light guide plate. The electrical connector is aligned with the through hole or further protrudes into the through hole.Type: ApplicationFiled: December 3, 2020Publication date: January 27, 2022Inventors: Hsuan-Wei HO, Yi-Ching WU
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Patent number: 11171608Abstract: The present invention is to provide a mixing circuit, comprising: a first transistor; a second transistor; a third transistor; a first connection point connected to a gate terminal of the first transistor, a drain terminal of the second transistor and a source terminal of the third transistor; a second connection point connected to a source terminal of the first transistor and a gate terminal of the second transistor; and a third connection point connected to a drain terminal of the first transistor and a drain terminal of the third transistor.Type: GrantFiled: December 6, 2019Date of Patent: November 9, 2021Assignee: ACADEMIA SINICAInventors: Yi-Ching Wu, Yuh-Jing Hwang, Chau-Ching Chiong, Bo-Ze Lu, Huei Wang
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Publication number: 20210320623Abstract: The present invention is to provide a mixing circuit, comprising: a first transistor; a second transistor; a third transistor; a first connection point connected to a gate terminal of the first transistor, a drain terminal of the second transistor and a source terminal of the third transistor; a second connection point connected to a source terminal of the first transistor and a gate terminal of the second transistor; and a third connection point connected to a drain terminal of the first transistor and a drain terminal of the third transistor.Type: ApplicationFiled: December 6, 2019Publication date: October 14, 2021Inventors: YI-CHING WU, YUH-JING HWANG, Chau-Ching Chiong, Bo-Ze Lu, HUEI WANG
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Publication number: 20160329504Abstract: Aromatic derivatives having an electron donating group and an electron accepting group at each end are provided. The aromatic derivatives of the present invention can emit blue or green light and may function as a host material or a dopant material. An OLED device using the aromatic derivatives is also herein disclosed.Type: ApplicationFiled: September 10, 2015Publication date: November 10, 2016Inventors: Chien-Hong CHENG, Chih-Chun LIN, Yi-Ching WU
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Patent number: 9378968Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.Type: GrantFiled: September 2, 2014Date of Patent: June 28, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yi-Ching Wu, Horng-Bor Lu, Yung-Chieh Kuo
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Publication number: 20160064241Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.Type: ApplicationFiled: September 2, 2014Publication date: March 3, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: YI-CHING WU, HORNG-BOR LU, YUNG-CHIEH KUO
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Patent number: 9064814Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.Type: GrantFiled: June 19, 2013Date of Patent: June 23, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
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Patent number: 9040315Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.Type: GrantFiled: June 19, 2013Date of Patent: May 26, 2015Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yi-Ching Wu, Tzu-Hung Yang, Chih-Chung Wu
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Patent number: 8921947Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.Type: GrantFiled: June 10, 2013Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Ching Wu
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Publication number: 20140374805Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
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Publication number: 20140377887Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Yi-Ching WU, Tzu-Hung Yang, Chih-Chung Wu
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Publication number: 20140361381Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Ching Wu
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Patent number: 8755646Abstract: A method of fabricating an optical transformer is provided. A substrate is provided first, wherein the substrate includes a first region and a second region. Then a first material layer is formed on the substrate, and the portion of the first material layer other than in the first region is removed. Then a second material layer is formed on the substrate, and the portion of the second material layer in the first region and the second region is removed. Lastly, a first conductive layer is formed on the substrate and the portion of the first conductive layer other than in the second region is removed to make the first material layer, the second material layer and the first conductive layer have the same height such that the first material layer becomes a part of the optical transformer. The present invention further provides a semiconductor structure.Type: GrantFiled: July 22, 2013Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Yi-Ching Wu, Shuenn-Jeng Chen