Patents by Inventor Yi-Chuan Teng

Yi-Chuan Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11851318
    Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu, Wei-Cheng Shen, Xin-Hua Huang, Wei-Chu Lin
  • Publication number: 20230382719
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
  • Publication number: 20230382718
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
  • Patent number: 11807520
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Chuan Teng, Ching-Kai Shen, Jung-Kuo Tu
  • Patent number: 11772960
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Patent number: 11730058
    Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
  • Publication number: 20230120504
    Abstract: A wafer includes a plurality of testing dies, a plurality of non-testing dies, and a dicing region. Each testing die includes: a first active area including one or more first active devices, and one or more first device pads electrically coupled to the one or more first active devices. Each non-testing die includes: a second active area including one or more second active devices, and one or more second device pads electrically coupled to the one or more second active devices. The dicing region includes one or more testing pads electrically coupled to the one or more first device pads. The one or more testing pads are arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies. The plurality of non-testing dies are electrically isolated from the dicing region.
    Type: Application
    Filed: September 12, 2022
    Publication date: April 20, 2023
    Inventors: Chien-Yu Chen, Yi-Chuan Teng, Yu-Hsuan Liu, Yun-Chung Na
  • Publication number: 20220411260
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: YI-CHUAN TENG, CHING-KAI SHEN, JUNG-KUO TU
  • Publication number: 20220384709
    Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
  • Patent number: 11516596
    Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Chu Lin, Yi-Chuan Teng, Jung-Kuo Tu
  • Publication number: 20220367378
    Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: CHING-KAI SHEN, YI-CHUAN TENG, WEI-CHU LIN, HUNG-WEI LIANG, JUNG-KUO TU
  • Publication number: 20220340408
    Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
  • Publication number: 20220340407
    Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chuan TENG, Ching-Kai SHEN, Jung-Kuo TU, Wei-Cheng SHEN, Xin-Hua HUANG, Wei-Chu LIN
  • Publication number: 20220315414
    Abstract: The present disclosure provides a semiconductor structure and a method for fabricating semiconductor structure. The semiconductor structure includes a first device, configured to be a complementary metal oxide semiconductor device, wherein the first device includes a substrate, a multi-layer structure disposed on the substrate, a first hole, defined between a first end with a first circumference and a second end with a second circumference, a second hole, aligned to the first hole and defined between the second end and a third end with a third circumference, wherein the third circumference is larger than the first circumference and the second circumference, and a second device, configured to be a micro-electro mechanical system device and bonded to the first device, wherein a first chamber is between the first device and the second device, and the first end links with the first chamber, and a sealing object configured to seal the second hole.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: CHUN-WEN CHENG, YI-CHUAN TENG, CHENG-YU HSIEH, LEE-CHUAN TSENG, SHIH-CHANG LIU, SHIH-WEI LIN
  • Patent number: 11462478
    Abstract: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Patent number: 11434129
    Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Cheng-Yu Hsieh, Lee-Chuan Tseng, Shih-Chang Liu, Shih-Wei Lin
  • Publication number: 20220227618
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a first dielectric layer formed over the substrate. The semiconductor device structure also includes a first movable membrane formed over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion and a first edge portion connecting to the first corrugated portion. The semiconductor device structure further includes a second dielectric layer formed over the first movable membrane. In addition, the first edge portion is sandwiched between the first dielectric layer and the second dielectric layer, the first corrugated portion is partially sandwiched between the first dielectric layer and the second dielectric layer and is partially exposed by a cavity, and a bottom surface of the first corrugated portion is lower than a bottom surface of the first edge portion.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 21, 2022
    Inventors: Yi-Chuan TENG, Chun-Yin TSAI, Chia-Hua CHU, Chun-Wen CHENG
  • Publication number: 20220194783
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 23, 2022
    Inventors: Yang-Che CHEN, Victor Chiang LIANG, Chen-Hua LIN, Chwen-Ming LIU, Huang-Wen TSENG, Yi-Chuan TENG
  • Publication number: 20220141596
    Abstract: A MEMS device and a method for manufacturing a MEMS device are provided. The MEMS device includes an anchor, a diaphragm structure, and a sealing film. The diaphragm structure is disposed over the anchor and has an opening through the diaphragm structure. The sealing film covers at least a portion of the opening of the diaphragm structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: WEI-CHU LIN, YI-CHUAN TENG, JUNG-KUO TU
  • Patent number: 11292712
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first dielectric layer over a substrate and forming a first recess in the first dielectric layer. The method also includes conformally forming a first movable membrane over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion in the first recess. The method further includes forming a second dielectric layer over the first movable membrane and partially removing the substrate, the first dielectric layer, and the second dielectric layer to form a cavity. In addition, the first corrugated portion of the first movable membrane is partially sandwiched between the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Chuan Teng, Chun-Yin Tsai, Chia-Hua Chu, Chun-Wen Cheng