Patents by Inventor Yi-Chuan Teng
Yi-Chuan Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9238578Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises one or more spring structures, such as a first spring structure and a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer, such as for CMOS outgassing relief. One or more thermal insulator structures are formed between the CMOS wafer and the MEMS wafer to protect the MEMS wafer from heat originating from the CMOS wafer.Type: GrantFiled: March 7, 2014Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Publication number: 20160002027Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.Type: ApplicationFiled: September 11, 2015Publication date: January 7, 2016Inventors: Chun-wen CHENG, Jung-Huei PENG, Shang-Ying TSAI, Hung-Chia TSAI, Yi-Chuan TENG
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Publication number: 20150329351Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.Type: ApplicationFiled: December 20, 2013Publication date: November 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Hung-Chia Tsai, Chia-Hua Chu
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Patent number: 9150404Abstract: A method of forming a semiconductor device having through molding vias includes eutectic bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches and a plurality of separation trenches having a depth greater than the isolation trenches with respect to a same surface of the capping wafer. The method also includes removing a portion of the capping wafer exposing a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package to separate the wafer package into a first chip package, a second chip package, and a third chip package.Type: GrantFiled: December 16, 2013Date of Patent: October 6, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
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Publication number: 20150274513Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Publication number: 20150251901Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises one or more spring structures, such as a first spring structure and a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer, such as for CMOS outgassing relief. One or more thermal insulator structures are formed between the CMOS wafer and the MEMS wafer to protect the MEMS wafer from heat originating from the CMOS wafer.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Publication number: 20150251900Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Patent number: 9130531Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers.Type: GrantFiled: March 27, 2014Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Patent number: 9114976Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief.Type: GrantFiled: March 7, 2014Date of Patent: August 25, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
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Publication number: 20150197419Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
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Publication number: 20150174700Abstract: According to an exemplary embodiment of the disclosure, a method of removing a waste part of a substrate is provided. The method includes: using a laser to partially drill the substrate to define the waste part; and applying megasonic vibration to the substrate to remove the waste part from the substrate.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: CHIN-YI CHO, YI-CHUAN TENG, SHANG-YING TSAI, LI-MIN HUNG, YAO-TE HUANG, JUNG-HUEI PENG
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Publication number: 20150166329Abstract: A method of forming a semiconductor device having through molding vias comprises eutectic bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer comprises a plurality of isolation trenches and a plurality of separation trenches having a depth greater than the isolation trenches with respect to a same surface of the capping wafer. The method also comprises removing a portion of the capping wafer exposing a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further comprises separating the wafer package to separate the wafer package into a first chip package, a second chip package, and a third chip package.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-wen CHENG, Jung-Huei PENG, Shang-Ying TSAI, Hung-Chia TSAI, Yi-Chuan TENG
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Publication number: 20150166331Abstract: A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.Type: ApplicationFiled: December 30, 2014Publication date: June 18, 2015Inventors: Chun-wen CHENG, Jung-Huei PENG, Shang-Ying TSAI, Hung-Chia TSAI, Yi-Chuan TENG
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Publication number: 20150123129Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Chin-Yi Cho
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Patent number: 8941152Abstract: A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.Type: GrantFiled: December 13, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
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Publication number: 20140294216Abstract: The present invention relates to a waterproof speaker use on ship, which also includes a screw and a nut used to combine a vibration board, a first rubber pad, a base seat, a connection board, and a top cover combining with a housing into a unit. The present invention is characterized in that a second rubber pad is provided between the vibration board and the top cover, which can seal the gap between the housing and the top cover that prevents from water leaking into the speaker perfectly.Type: ApplicationFiled: March 27, 2013Publication date: October 2, 2014Inventor: YI-CHUAN TENG
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Patent number: 8841201Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.Type: GrantFiled: February 20, 2013Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Hsin-Ting Huang, Lin-Min Hung, Yao-Te Huang, Chin-Yi Cho
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Publication number: 20140220735Abstract: A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Hsin-Ting Huang, Li-Min Hung, Yao-Te Huang, Chin-Yi Cho
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Patent number: 8686571Abstract: A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.Type: GrantFiled: August 9, 2012Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Yi-Chuan Teng, Chin-Yi Cho
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Publication number: 20140042625Abstract: A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Yi-Chuan Teng, Chin-Yi Cho