Patents by Inventor Yi-Chun Lo
Yi-Chun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170358653Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: ApplicationFiled: August 25, 2017Publication date: December 14, 2017Inventors: Bo-Wen HSIEH, Wen-Jia HSIEH, Yi-Chun LO, Mi-Hua LIN
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Patent number: 9748350Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: GrantFiled: October 30, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
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Publication number: 20170221757Abstract: Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Wen-Jia Hsieh, Yi-Chun Lo
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Publication number: 20170189865Abstract: The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein A1 is A2 is R1 and R2 are independently —H, —CF3, —OH, —Br, —Cl, —F, C1-6 alkyl group, or C1-6 alkoxy group; and X and Y are independently single bond, —O—, —CH2—, —C(CH3)2—, or —NH—.Type: ApplicationFiled: July 18, 2016Publication date: July 6, 2017Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Rui-Xuan DONG, Shu-Hui CHENG, Jen-You CHU, Yin-Ju YANG, Yi-Chun LO
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Publication number: 20170154972Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: ApplicationFiled: October 13, 2016Publication date: June 1, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Wen HSIEH, Wen-Jia HSIEH, Yi-Chun LO
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Publication number: 20170125534Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Wen HSIEH, Wen-Jia HSIEH, Yi-Chun LO, Mi-Hua LIN
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Patent number: 9496367Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.Type: GrantFiled: December 22, 2015Date of Patent: November 15, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Chun Wang, Yi-Chun Lo, Chia-Der Chang, Guo-Chiang Chi, Chia-Ping Lo, Fu-Kai Yang, Hung-Chang Hsu, Mei-Yun Wang
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Publication number: 20160212772Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.Type: ApplicationFiled: March 17, 2015Publication date: July 21, 2016Inventors: CHIH-CHUN CHEN, YI-CHUN LO
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Publication number: 20160190249Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: WEN-JIA HSIEH, HSIN-HUNG CHEN, YI-CHUN LO, JUNG-YOU CHEN
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Publication number: 20160118471Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.Type: ApplicationFiled: December 22, 2015Publication date: April 28, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tien-Chun WANG, Yi-Chun LO, Chia-Der CHANG, Guo-Chiang CHI, Chia-Ping LO, Fu-Kai YANG, Hung-Chang HSU, Mei-Yun WANG
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Patent number: 9231098Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.Type: GrantFiled: October 30, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Chun Wang, Yi-Chun Lo, Chia-Der Chang, Guo-Chiang Chi, Chia-Ping Lo, Fu-Kai Yang, Hung-Chang Hsu, Mei-Yun Wang
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Publication number: 20150115335Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tien-Chun WANG, Yi-Chun LO, Chia-Der CHANG, Guo-Chiang CHI, Chia-Ping LO, Fu-Kai YANG, Hung-Chang HSU, Mei-Yun WANG
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Patent number: 8567611Abstract: The invention discloses a filtration material for desalination, including a support layer, and a desalination layer formed on the support layer, wherein the desalination layer is a fiber composite membrane and includes at least one water-swellable polymer. The water-swellable polymer is made of hydrophilic monomers and hydrophobic monomers, and the hydrophilic monomers include ionic monomers and non-ionic monomers, and the ionic monomers include cationic monomers and anionic monomers.Type: GrantFiled: December 21, 2010Date of Patent: October 29, 2013Assignee: Industrial Technology Research InstituteInventors: Shu-Hui Cheng, Jong-Pyng Chen, En Kuang Wang, Yi-Chun Lo, Shan-Shan Lin
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Publication number: 20130007724Abstract: A firmware repairing method for customer premises equipment (CPE) is illustrated. The method includes reading and detecting whether a first firmware is damaged, reading and loading a second firmware so as to activate network services when the first firmware damaged, and enabling communication between the CPE and an external device via a network. The CPE may be controlled by the external device for executing a repairing grogram and may receive an updated firmware from the external device for replacing the damaged first firmware.Type: ApplicationFiled: January 30, 2012Publication date: January 3, 2013Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: Yan-Cheng LAI, Yi-Chun LO
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Publication number: 20110210064Abstract: The invention discloses a filtration material for desalination, including a support layer, and a desalination layer formed on the support layer, wherein the desalination layer is a fiber composite membrane and includes at least one water-swellable polymer. The water-swellable polymer is made of hydrophilic monomers and hydrophobic monomers, and the hydrophilic monomers include ionic monomers and non-ionic monomers, and the ionic monomers include cationic monomers and anionic monomers.Type: ApplicationFiled: December 21, 2010Publication date: September 1, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shu-Hui Cheng, Jong-Pyng Chen, En Kuang Wang, Yi-Chun Lo, Shan-Shan Lin