Patents by Inventor Yi-Fan Chang

Yi-Fan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit
    Publication number: 20130100745
    Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
    Type: Application
    Filed: December 7, 2012
    Publication date: April 25, 2013
    Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen Long Chang, Chun-Hsiung Hung
  • Method and apparatus of performing an erase operation on a memory integrated circuit
    Patent number: 8339861
    Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: December 25, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen-Long Chang, Chun-Hsiung Hung
  • Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit
    Publication number: 20120300553
    Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Method and apparatus of performing an erase operation on a memory integrated circuit
    Patent number: 8259499
    Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: September 4, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit
    Publication number: 20110317493
    Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit
    Publication number: 20110128791
    Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
    Type: Application
    Filed: July 12, 2010
    Publication date: June 2, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen-Long Chang, Chun-Hsiung Hung