Abstract: A branch vessel stent including a stent body and a first developing member, where the first developing member includes a first developing portion and a second developing portion. A length of the first developing portion and a length of the second developing portion in an axial direction of the stent body are both not less than 0.5 mm. A distance between the intersections of the first developing portion and the second developing portion on a plane perpendicular to the axial direction of the stent body gradually increases from a position where the distance is the minimum distance to an end that is away from a first end of the first developing portion or the second developing portion. The minimum distance between the intersections of the first developing portion and the second developing portion on a plane perpendicular to the axial direction of the stent body is less than 2 mm.

Abstract: A ferroelectric device includes an electrode, another electrode, and a ferroelectric structure between the electrode and the another electrode. The ferroelectric structure includes one or more portions of bismuth oxide, and one or more portions of at least one metal oxide comprising hafnium-containing oxide, zirconium-containing oxide, or a combination thereof. A ferroelectric memory cell includes a source region, a drain region, and a capacitor in electrical communication with the drain region. The capacitor includes an electrode and a ferroelectric structure neighboring the electrode. The ferroelectric structure includes a first material comprising a first metal oxide, a second material comprising bismuth oxide, and a third material comprising a second metal oxide. The ferroelectric structure also includes a dopant in an amount of between about 0.1 atomic percent and about 25.0 atomic percent based on non-oxygen atoms of the ferroelectric structure.

Abstract: An electronic lock device includes a lock mechanism, an actuation mechanism that actuates the lock mechanism, and a control unit including a processor and a current detection module. During an operation in which the actuation mechanism is activated to start switching the lock mechanism from an original state to an intended state, the current detection module continuously detects an amount of electric current flowing through the actuation mechanism. When the amount of electric current is greater than a predetermined threshold, the processor controls the actuation mechanism to switch the lock mechanism back to the original state, and deactivates the actuation mechanism.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A training method based on an improved protograph neural decoder includes the following steps: a to-be-trained decoding network is constructed based on an initial variable sub-network layer, an initial check sub-network layer and a preset shuffled belief-propagation (BP) sub-network layer; the initial variable sub-network layer, the initial check sub-network layer and the preset shuffled BP sub-network layer are updated and trained by calculating log-likelihood ratio (LLR) based on a preset mean square error loss function and a preset decoder objective function to obtain a target protograph neural decoder; and the preset mean square error loss function is configured to calculate a loss value between output information of the check sub-network layer and the preset shuffled BP sub-network layer. The target protograph neural decoder includes an optimized variable sub-network layer, an optimized check sub-network layer and an optimized shuffled BP sub-network layer. A training device is also provided.

Abstract: A method of forming an apparatus comprises forming a crystalline semiconductor material comprising one or more of a monocrystalline material and a nanocrystalline material adjacent to active areas of memory cells, forming an amorphous material within portions of the crystalline semiconductor material, forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material, converting a portion of the amorphous material and the metal material to form a metal silicide material adjacent to the crystalline semiconductor material, forming cell contacts over the metal silicide material, and forming a storage node adjacent to the cell contacts. Additional methods and apparatus are also disclosed.

Abstract: Provided herein are systems and methods for configuring data recovery. A method includes decoding, by at least one hardware processor, a request to recover historical table data. The request is received from an account of a data provider. The historical table data includes a plurality of partition files. Each of the plurality of partition files includes a deleted file designation. Based on the request, a recovery process of the plurality of partition files is performed to obtain recovered partition files. A schema associated with the historical table data is retrieved. Metadata corresponding to the retrieved schema is generated. The metadata is associated with the recovered partition files to recover the historical table data.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Abstract: A differential chaos shift keying (DCSK) communication method based on three-dimensional constellation is provided. Target information bit is mapped to a three-dimensional constellation symbol. An initial chaotic signal generated by a chaotic generator is processed by cyclic shift to generate a chaotic signal group including the initial chaotic signal, a first shifted chaotic signal and a second shifted chaotic signal. Information modulation is performed based on the three-dimensional constellation symbol and the chaotic signal group to obtain an information-bearing signal. A transmission signal is generated based on the information-bearing signal and the initial chaotic signal, and sent to a receiver to generate a received signal, which is subjected to information recovery analysis in the receiver to obtain an estimated information bit. A DCSK communication device based on three-dimensional constellation is also provided.

Abstract: A cutting element may include a body, a concave cutting face formed at a first end of the body, the cutting face including one or more cutting ridges adjacent a cutting tip that are raised above the concavity of the cutting face and having a length that is at least about 10% of a diameter of the cutting face. An edge is formed around a perimeter of the cutting face, and the edge has an edge angle defined between a tangent of the cutting face and a cylindrical side surface of the body, the edge angle being acute at the cutting tip and varying around the perimeter of the cutting face.

Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.

Abstract: A drilling tool having a body, at least one blade extending from the body, and a first cutting element attached to the at least one blade. The first cutting element includes a cutting face at an opposite axial end from a base, a side surface extending from the base to the cutting face, an edge formed at the intersection between the cutting face and the side surface, and an elongated protrusion formed at the cutting face and extending between opposite sides of the edge. The elongated protrusion has a geometry including a border extending around a concave surface, a face chamfer formed around the border, and sloped surfaces extending between the border and the edge. An edge chamfer is between the face chamfer and the edge.

Abstract: A covered stent (100A), including a mesh-shaped support structure, and further including a first section (10A) and a second section (20A) connected to a proximal end and/or a distal end of the first section. The first section includes a plurality of first corrugated rings (11A), and a first covering film (12A) which covers surfaces of the first corrugated rings; the second section includes a plurality of second corrugated rings (21A), two adjacent second corrugated rings being fixedly connected to each other; a plurality of windows (201A) are formed between the plurality of second corrugated rings; and the plurality of first corrugated rings and the plurality of second corrugated rings form the support structure.

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.