Patents by Inventor Yi Feng

Yi Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146685
    Abstract: System and techniques for capability discovery in an information centric network (ICN) are described herein. An ICN node receives a discovery packet that includes a discovery type corresponding to an indication of a node capability requested by a source node of the discovery packet. First capability data, from an intermediate node, is extracted from the discovery packet. The first capability data is stored locally by ICN node. Second capability data from the ICN node is added to the discovery packet to create an expanded discovery packet. The expanded discovery packet is then communicated by the ICN node.
    Type: Application
    Filed: December 23, 2021
    Publication date: May 2, 2024
    Inventors: Yi Zhang, Srikathyayani Srikanteswara, Hao Feng, Nageen Himayat, Gabriel Arrobo
  • Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 11966677
    Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 23, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Melvyn Goveas, Ribhu Mittal, Wen-Chi Feng, Yanhua Yi
  • Patent number: 11966352
    Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
  • Patent number: 11963868
    Abstract: A double-sided aspheric diffractive multifocal lens and methods of manufacturing and design of such lenses in the field of ophthalmology. The lens can include an optic comprising an aspheric anterior surface and an aspheric posterior surface. On one of the two surfaces a plurality of concentric diffractive multifocal zones can be designed. The other surface can include a toric component. The double-sided aspheric surface design results in improvement of the modulation transfer function (MTF) of the lens-eye combination by aberration reduction and vision contrast enhancement as compared to one-sided aspheric lens. The surface having a plurality of concentric diffractive multifocal zones produces a near focus, an intermediate focus, and a distance focus.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 23, 2024
    Assignee: AST Products, Inc.
    Inventors: Yi-Feng Chiu, Chuan-Hui Yang, Wen-Chu Tseng
  • Publication number: 20240122547
    Abstract: A human-body-signal collection device (10). The human-body-signal collection device (10) includes a reference electrode (210), a first electrode (220) and a second electrode (230), an adjusting and generating device (30), a first collection device (40), and a first feedback device (50). The first electrode (220) outputs the first signal. The second electrode (230) outputs the second signal. The adjusting and generating device (30) is connected to the reference electrode (210) to output a reference signal to the reference electrode (210). The first collection device (40) collects the first signal and the second signal, and generates a first potential-difference signal based on the first signal and the second signal. The first feedback device (50) is connected to the first collection device (40) and the adjusting and generating device respectively.
    Type: Application
    Filed: August 30, 2021
    Publication date: April 18, 2024
    Inventors: ZHUO-BIAO HE, JUN TIAN, YI-FENG CHEN, DUN ALEX LI
  • Publication number: 20240124827
    Abstract: The present invention provides a device for enrichment culture and gravity-type isolation of marine microorganisms in a high-pressure environment. The device includes an enrichment and multistage purification unit and a gravity-type isolation and culture unit. Under a high-pressure and low-temperature environment constructed to be consistent with a marine environment, the enrichment and multistage purification unit is used for realizing a process of enrichment and multistage purification of the marine microorganisms, obtaining a marine microorganism enrichment bacteria liquid and injecting the marine microorganism enrichment bacteria liquid into the gravity-type isolation and culture unit. The gravity-type isolation and culture unit is used for carrying out automatic streaking by means of gravity in the high-pressure environment to achieve solid isolation and culture of the marine microorganisms, such that culturability of the marine microorganisms is effectively improved.
    Type: Application
    Filed: March 30, 2022
    Publication date: April 18, 2024
    Applicants: GUANGDONG LABORATORY OF SOUTHERN OCEAN SCIENCE AND ENGINEERING (GUANGZHOU), GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Jingchun FENG, Si ZHANG, Zhifeng YANG, Yi WANG, Yanpeng CAI, Song ZHONG
  • Publication number: 20240126314
    Abstract: A low dropout regulator includes output terminal circuit and amplifier. The output terminal circuit is configured to generate output voltage according to input voltage and is configured to generate feedback voltage according to the output voltage. The amplifier is configured to generate control voltage to the output terminal circuit according to reference voltage and the feedback voltage, so as to adjust the output voltage, wherein the amplifier includes input stage circuit, current mirror circuit and filter circuit. The input stage circuit is configured to receive the reference voltage and the feedback voltage to generate a differential output. The filter circuit is configured to filter the input voltage to generate dependent current related to noise of the input voltage on the current mirror circuit, wherein the current mirror circuit is configured to output the control voltage according to the differential output and the dependent current.
    Type: Application
    Filed: March 9, 2023
    Publication date: April 18, 2024
    Inventors: Yi FENG, Hsueh-Yu KAO
  • Patent number: 11961546
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Patent number: 11961609
    Abstract: The disclosure provides a three-dimensional (3D) image classification method and apparatus, a device, and a storage medium. The method includes: obtaining a 3D image, the 3D image including first-dimensional image information, second-dimensional image information, and third-dimensional image information; extracting a first image feature corresponding to planar image information from the 3D image; extracting a second image feature corresponding to the third-dimensional image information from the 3D image; fusing the first image feature and the second image feature, to obtain a fused image feature corresponding to the 3D image; and determining a classification result corresponding to the 3D image according to the fused image feature corresponding to the 3D image.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: April 16, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yi Fan Hu, Ye Feng Zheng
  • Publication number: 20240120316
    Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
  • Publication number: 20240120306
    Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.
    Type: Application
    Filed: November 4, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
  • Patent number: 11953774
    Abstract: A display substrate includes: a base substrate (100); a plurality of sub-pixels (R, G, B) located on the base substrate (100), every two rows of sub-pixels (R, G, B) constituting a pixel group; a plurality of first gate lines (Gate1) located at first row gaps between the pixel groups, two first gate lines (Gate1) being arranged at each first row gap; and a plurality of photosensors (101), the orthographic projection of each row of photosensors (101) on the base substrate (100) completely covering a second row gap in the pixel group and partially overlapping with the orthographic projections of the sub-pixels (R, G, B), thereby avoiding the bright and dark difference between adjacent rows and ensuring the aperture ratio.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 9, 2024
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xinlan Yang, Wenkai Mu, Yi Liu, Jun Fan, Bo Feng, Yang Wang, Zhan Wei, Tengfei Ding, Shijun Wang, Chengfu Xu
  • Patent number: 11953114
    Abstract: An air valve with a SMA wire for switching is located in an air chamber in which at least two air holes are formed. The air valve comprises a base, an air piston, a driving component, and the SMA wire. The base is provided with two supporting blocks, and two conduction components near one of the two supporting blocks. The air piston determines a ventilation state of one of the two air holes. The air piston comprises a rod body on the two supporting blocks and with a first triggering part, and a spring sleeved on the rod body. The driving component is sleeved on the rod body and with a second triggering part matched with the first triggering part. The SMA wire is connected with the two conduction components and the driving component, and is turned by the supporting block opposite to the two conduction components.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: April 9, 2024
    Assignee: TANGTRING SEATING TECHNOLOGY INC.
    Inventors: Jian Zeng, Jun Xie, Qing-Yi Feng
  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240113140
    Abstract: A ridge recognition substrate and a ridge recognition apparatus. The ridge recognition substrate includes: a base substrate including a photosensitive area, and a light-shielding area located on at least one side of the photosensitive area; a plurality of photosensitive devices, arranged in the photosensitive area in an array; each photosensitive device includes a first electrode, a photoelectric conversion structure and a second electrode arranged in layers, the photoelectric conversion structure is electrically connected with the first electrode, and the photoelectric conversion structure directly contacts with the second electrode; and dummy devices, arranged in the light-shielding area in an array, each dummy device including a third electrode, an equivalent dielectric layer and a fourth electrode, the third electrode and the first electrode is in the same layer, the fourth electrode is located at the side of the layer where the second electrode is located facing away from the base substrate.
    Type: Application
    Filed: May 26, 2021
    Publication date: April 4, 2024
    Inventors: Yajie FENG, Cheng LI, Yue GENG, Kuiyuan WANG, Zhonghuan LI, Yi DAI, Chaoyang QI, Zefei LI, Congcong XI, Xiaoguan LI
  • Publication number: 20240113044
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventor: Yi-Feng Chang
  • Patent number: 11945271
    Abstract: A rigid-flexible coupling multi-degree-of-freedom walking position-adjusting leg unit and a hybrid robot platform thereof is provided and includes a vertical rigid-flexible coupling multi-degree-of-freedom walking position-adjusting leg unit and a horizontal rigid-flexible coupling multi-degree-of-freedom walking position-adjusting leg unit, which both include a moving device, a moving drive, a steering frame, a lifting frame, a spring device and a driving differential wheel set, in combination with a frame, a driver set, a battery pack and a control box, forming a multi-degree-of-freedom parallel mechanism platform. The hybrid robot platform including the rigid-flexible coupling multi-degree-of-freedom walking position-adjusting leg unit as provided by the present disclosure has functions of a rigid position adjustment, an elastic suspension and a rigid-flexible coupling position adjustment, and can automatically adapt to a working condition of the uneven ground.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 2, 2024
    Assignee: YANSHAN UNIVERSITY
    Inventors: Yulin Zhou, Shuyang Shi, Lihui Zhao, Xuesong Qiu, Zongqiang Feng, Yi Liu
  • Patent number: D1025064
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Logitech Europe S.A.
    Inventors: Yi-Hsuan Lin, Blaithin Crampton, Marcel Twohig, Anish Shakthi Ovia Selvan, Anatoliy Polyanker, Jingyan Ma, Ming Feng Hsieh, Olivia Hildebrand