Patents by Inventor Yi-Feng Chang

Yi-Feng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424185
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Chia-Hung Chu, Kao-Feng Lin, Hsu-Kai Chang, Shuen-Shin Liang, Sung-Li Wang, Yi-Ying Liu, Po-Nan Yeh, Yu Shih Wang, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh
  • Patent number: 11416666
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes obtaining an IC design; generating a layout according to the IC design; calculating a score of a region in the layout based on voltage levels in the region; and fabricating a semiconductor device according to the layout when the score of the region in the layout is equal to or less than a threshold value.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Fang Lai, Guan-Yu Chen, Yi-Feng Chang
  • Publication number: 20220230884
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Publication number: 20220223727
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 14, 2022
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20220208751
    Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 18, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Jam-Wem LEE
  • Publication number: 20220165725
    Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Publication number: 20220130825
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Publication number: 20220130824
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Patent number: 11282830
    Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 11222893
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11127546
    Abstract: A keyboard includes an elastic element disposed above a bottom case, a light emitter, a light receiver, a pressing element, and a keycap. When a force toward the bottom case is applied to a top surface of the elastic element, a relationship between a force to move the top surface and a distance from the top surface to the bottom case is in a negative correlation in a path of the top surface from a first position to a second position, and a relationship between a force to move the top surface and a distance from the top surface to the bottom case is in a positive correlation in a path of the top surface from the second position to a third position. The light emitter, the light receiver, and the pressing element are disposed above the elastic element. The keycap is disposed above the pressing element.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Chicony Electronics Co., Ltd.
    Inventors: Tao-Kuan Chen, Tzu-Chuan Liang, Yi-Feng Chang
  • Patent number: 10930640
    Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee, Li-Wei Chu, Po-Lin Peng
  • Patent number: 10867987
    Abstract: An integrated circuit device with ESD protection includes a substrate with a well having a first conductivity type formed on the substrate. A drain region has at least one drain diffusion with a second conductivity type implanted in the well and at least one drain conductive insertion on the well. The drain conductive insertion is electrically connected to the drain diffusion and an I/O pad. A source region includes a plurality of source diffusions having the second conductivity type implanted in the well, and the source diffusions are electrically connected to a voltage terminal.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 15, 2020
    Inventors: Po-Lin Peng, Li-Wei Chu, Yi-Feng Chang, Jam-Wem Lee
  • Publication number: 20200373255
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 26, 2020
    Inventor: Yi-Feng Chang
  • Publication number: 20200365529
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventor: Yi-Feng Chang
  • Publication number: 20200365349
    Abstract: A keyboard includes an elastic element disposed above a bottom case, a light emitter, a light receiver, a pressing element, and a keycap. When a force toward the bottom case is applied to a top surface of the elastic element, a relationship between a force to move the top surface and a distance from the top surface to the bottom case is in a negative correlation in a path of the top surface from a first position to a second position, and a relationship between a force to move the top surface and a distance from the top surface to the bottom case is in a positive correlation in a path of the top surface from the second position to a third position. The light emitter, the light receiver, and the pressing element are disposed above the elastic element. The keycap is disposed above the pressing element.
    Type: Application
    Filed: October 28, 2019
    Publication date: November 19, 2020
    Inventors: Tao-Kuan CHEN, Tzu-Chuan LIANG, Yi-Feng CHANG
  • Publication number: 20200365531
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventor: Yi-Feng Chang
  • Publication number: 20200258878
    Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Feng CHANG, Jam-Wem LEE, Li-Wei CHU, Po-Lin PENG
  • Patent number: 10734330
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Yi-Feng Chang
  • Patent number: D963688
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 13, 2022
    Assignee: GOGORO INC.
    Inventors: Chuan-feng Yeh, Yi-wen Chang, Chih-min Fu, Kai-wen Cheng