Patents by Inventor Yi-Hao Chen
Yi-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11681647Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.Type: GrantFiled: July 3, 2020Date of Patent: June 20, 2023Assignee: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng Kuang Hsieh
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Patent number: 11624985Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.Type: GrantFiled: October 5, 2020Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
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Publication number: 20230076006Abstract: A control system and a control method are provided. The control system provides a first setting signal in response to an abnormal read-write operation performed on at least one storage device. The control system generates a first state signal having a first logic value in response to the first setting signal and latches the first state signal, and disables the at least one storage device on which the abnormal read-write operation is performed in response to the first state signal having the first logic value. The control system includes a restart input module. The restart input module converts the first logic value of the latched first state signal into a second logic value, so that the control system restarts the at least one storage device disabled in response to the first state signal having the second logic value.Type: ApplicationFiled: November 18, 2021Publication date: March 9, 2023Applicant: Wiwynn CorporationInventors: Yahsuan Tseng, Kai-Sheng Chen, Yi-Hao Chen, Chung Fu Huang
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Publication number: 20230014174Abstract: An environment detecting module, for securing a shell of a server, includes a sensing module, configured to sense an environment status by a polling method and generate a sensing signal according to the environment status; a connection module, configured to electrically connect the environment detecting module to a host terminal with a first connection status or a second connection status; and a microcontroller unit, coupled to the sensing module and the connection module, configured to determine a power source of the environment detecting module according to the first connection status or the second connection status, and to determine a first mode or a second mode of the environment detecting module according to the power source.Type: ApplicationFiled: September 27, 2021Publication date: January 19, 2023Applicant: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng-Kuang Hsieh, Yung-Ti Chung, Jheng-Ying Jiang
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Patent number: 11302686Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.Type: GrantFiled: November 18, 2019Date of Patent: April 12, 2022Assignee: Nuvoton Technology CorporationInventors: Yi-Hao Chen, Tsu-Yi Wu, Chih-Hsun Lu, Po-An Chen, Chun-Chieh Liu
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Publication number: 20210357349Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.Type: ApplicationFiled: July 3, 2020Publication date: November 18, 2021Applicant: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng Kuang Hsieh
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Publication number: 20210305233Abstract: A semiconductor device for protecting an internal circuit includes a transistor, a first doping region, and a second doping region. The transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is coupled to a ground. The source terminal is coupled to the internal circuit. The drain terminal is coupled to an input/output pad. The first doping region has a first conductive type. The second doping region has a second conductive type and is adjacent to the first doping region. The first doping region and the second doping region form the gate terminal. The first conductive type is different from the second conductive type.Type: ApplicationFiled: March 2, 2021Publication date: September 30, 2021Inventor: Yi-Hao CHEN
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Publication number: 20210035969Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.Type: ApplicationFiled: November 18, 2019Publication date: February 4, 2021Inventors: Yi-Hao CHEN, Tsu-Yi WU, Chih-Hsun LU, Po-An CHEN, Chun-Chieh LIU
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Publication number: 20210018848Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Ta-Ching YU, Shih-Che WANG, Shu-Hao CHANG, Yi-Hao CHEN, Chen-Yen KAO, Te-Chih HUANG, Yuan-Fu HSU
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Patent number: 10795388Abstract: A voltage adjustment device comprises a voltage detector and a signal emitter. The voltage detector electrically connects to an electrical device through a power rail and obtains a voltage detected value of the power rail. The signal emitter electrically connects to the voltage detector and is configured to electrically connect to a host and a power board. The signal emitter generates a power good signal and sends the power good signal to the host when the voltage detected value is larger than a baseline voltage value for the first time. After sending the power good signal, the signal emitter generates a voltage adjustment signal according to the voltage detected value and is configured to send the voltage adjustment signal to the power board for selectively adjusting a voltage provided by the power board.Type: GrantFiled: September 12, 2018Date of Patent: October 6, 2020Assignee: WIWYNN CORPORATIONInventors: Yi-Hao Chen, Chia-Ming Tsai
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Patent number: 10795270Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.Type: GrantFiled: December 6, 2017Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
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Patent number: 10777539Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.Type: GrantFiled: September 26, 2019Date of Patent: September 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang
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Publication number: 20200272041Abstract: An actuator module and a projector having the same are provided. The actuator module includes an actuator including a frame and a lens movably disposed on the frame, and a pair of weighted blocks disposed on the frame and located at two opposite sides of the lens.Type: ApplicationFiled: February 7, 2020Publication date: August 27, 2020Applicant: Qisda CorporationInventors: PO-FU WU, YI-HAO CHEN
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Patent number: 10754400Abstract: A control method for data storage system includes obtaining a correlation coefficient corresponding to storage devices using a control device, and adjusting the link speed of one of the storage devices using the control device.Type: GrantFiled: December 12, 2018Date of Patent: August 25, 2020Assignee: WIWYNN CORPORATIONInventors: Cheng Kuang Hsieh, Kai Sheng Chen, Chia Ming Tsai, Yi-Hao Chen
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Patent number: 10594365Abstract: A server device and a power management method for the server device are provided. The server device includes a power supply device, a power transmission path, and at least one electronic device. The power supply device includes a first power line communication (PLC) transceiver. The at least one electronic device is coupled to the power transmission path to obtain power from the power supply device. The at least one electronic device includes a second PLC transceiver. The at least one electronic device utilizes the second PLC transceiver to communicate with the first PLC transceiver in the power supply device through the power transmission path to obtain an operation status of the power supply device and control the power supply device.Type: GrantFiled: February 18, 2019Date of Patent: March 17, 2020Assignee: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng-Kuang Hsieh
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Publication number: 20200057478Abstract: A control method for data storage system includes obtaining a correlation coefficient corresponding to storage devices using a control device, and adjusting the link speed of one of the storage devices using the control device.Type: ApplicationFiled: December 12, 2018Publication date: February 20, 2020Inventors: Cheng Kuang HSIEH, Kai Sheng CHEN, Chia Ming TSAI, Yi-Hao CHEN
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Publication number: 20200027860Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.Type: ApplicationFiled: September 26, 2019Publication date: January 23, 2020Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang
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Publication number: 20190391607Abstract: A voltage adjustment device comprises a voltage detector and a signal emitter. The voltage detector electrically connects to an electrical device through a power rail and obtains a voltage detected value of the power rail. The signal emitter electrically connects to the voltage detector and is configured to electrically connect to a host and a power board. The signal emitter generates a power good signal and sends the power good signal to the host when the voltage detected value is larger than a baseline voltage value for the first time. After sending the power good signal, the signal emitter generates a voltage adjustment signal according to the voltage detected value and is configured to send the voltage adjustment signal to the power board for selectively adjusting a voltage provided by the power board.Type: ApplicationFiled: September 12, 2018Publication date: December 26, 2019Applicant: WIWYNN CORPORATIONInventors: Yi-Hao CHEN, Chia-Ming TSAI
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Patent number: 10475772Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.Type: GrantFiled: December 11, 2018Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang
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Publication number: 20190109121Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.Type: ApplicationFiled: December 11, 2018Publication date: April 11, 2019Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang