Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.

Abstract: A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.

Abstract: A lighting device includes a base, a light emitting component operable to generate light, and a light control component cooperating with the base to enclose the light emitting component. The light control component includes a light transmissive body that has a datum point, a main axis passing through the datum point, a light incident surface that is axis symmetrical relative to the main axis, and a light exit surface that is axis symmetrical relative to the main axis. The light incident surface includes a plurality of annular incident surface portions that form a Fresnel lens configuration and that are concentric with respect to the main axis.

Abstract: A lighting device includes a base, a light emitting component operable to generate light, and a light control component cooperating with the base to enclose the light emitting component. The light control component includes a light transmissive body that has a datum point, a main axis passing through the datum point, a light incident surface that is axis symmetrical relative to the main axis, and a light exit surface that is axis symmetrical relative to the main axis. The light incident surface includes a plurality of annular incident surface portions that form a Fresnel lens configuration and that are concentric with respect to the main axis.

Abstract: A surface plasmon resonance meter is provided, including a backlight module, a line-slot plate, a parabolic mirror, a linear polarizer, a sensing chip, a prism and a photo detector array. The line-slot plate includes a light outlet. A light beam travels in the backlight module, and leaves the backlight module through the light outlet. The position of the line-slot plate is matched on a predetermined focal point of the parabolic mirror. The light beam is reflected by the parabolic mirror to be a parallel light beam, and travels trough the linear polarizer to the prism. The prism includes a light entering surface, a detection surface and a light exiting surface. The light beam enters the prism through the light entering surface, contacts the sensing chip with total internal reflection, and finally leaves the prism through the light exiting surface to be received by the photo detector array.

Abstract: A surface plasmon resonance meter is provided, including a backlight module, a line-slot plate, a parabolic mirror, a linear polarizer, a sensing chip, a prism and a photo detector array. The line-slot plate includes a light outlet. A light beam travels in the backlight module, and leaves the backlight module through the light outlet. The position of the line-slot plate is matched on a predetermined focal point of the parabolic mirror. The light beam is reflected by the parabolic mirror to be a parallel light beam, and travels trough the linear polarizer to the prism. The prism includes a light entering surface, a detection surface and a light exiting surface. The light beam enters the prism through the light entering surface, contacts the sensing chip with total internal reflection, and finally leaves the prism through the light exiting surface to be received by the photo detector array.