Abstract: Some embodiments relate to a memory cell, including: a write transistor on a substrate and comprising a first gate terminal, a first source/drain region, and a second source/drain region coupled to a storage node; a first read transistor on the substrate and comprising a second gate terminal coupled to the storage node and a gate dielectric with a first capacitance; and a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and has a second capacitance that is over twice the first capacitance.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A neural network circuit includes an input neuron layer comprises a plurality of first neurons. A hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. The probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. A weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.

Abstract: A mounting assembly is provided for mounting a liquid cooling adaptor manifold to a server rack. The mounting assembly includes the liquid cooling adaptor, a mounting adaptor, and a mounting bracket. The liquid cooling adaptor provides a cooling liquid from a source via first connectors of a first type to a device via second connectors of a second type. The mounting adaptor is affixed to the liquid cooling adaptor manifold and to the mounting bracket. The mounting bracket is affixed to a side wall of a server rack.

Abstract: A gait monitoring and healthcare system includes a first IMU, a second IMU and a local host. The first IMU senses an activity state of a thigh and generates a first activity signal. The second IMU senses an activity state of a calf and generates a second activity signal. The local host includes a microprocessor and an alarm. The microprocessor performs operations of: calculating a first pitch angle between a horizontal plane and the first IMU, and a second pitch angle between the horizontal plane and the second IMU according to the first and second activity signals; calculating activity information of a knee joint, including a bending angle, according to the first and second pitch angles; and judging whether the bending angle of the knee joint falls within a dangerous range according to the activity information, and controlling the alarm to output a warning signal if yes.

Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: A cable management system for a server rack, including an adapter bracket coupled to the server rack; a rail assembly coupled to the adapter bracket, the rail assembly including a plurality of apertures; a cable management apparatus slideably coupled to the rail assembly, the cable management apparatus including: a plunger; a plurality of tabs; and a plurality of retention devices, wherein, when the cable management apparatus is coupled to the rail assembly, the plunger extends through one of the apertures to define a position of the cable management apparatus with respect to the rail assembly such that one or more cables of the server rack are positioned between opposing tabs of the plurality of tabs and coupled to the cable management apparatus by one or more of the retention devices.

Abstract: A server rack includes a frame and a top panel. The frame includes a top frame structure and holds multiple information handling systems. The top panel includes a main portion and a sliding portion. The main portion is secured in a fixed location on the top frame structure. The sliding portion is adjustably coupled to a first edge of the main portion. The sliding portion transitions between a closed portion and an open position. A space between the sliding portion and an outer edge of the top frame structure is larger when the sliding portion is in the open position as compared to when the sliding portion is in the closed position.

Abstract: In some embodiments, the present disclosure provides an integrated chip including a first electrode made of a metal; a second electrode disposed over the first electrode; a ferroelectric layer between the first and second electrodes; and an interfacial layer separating the ferroelectric layer and the first electrode, the interfacial layer comprising a semiconductor material and configured to space the first electrode from the ferroelectric layer.

Abstract: A semiconductor structure according to the present disclosure includes a conductive feature in a top portion of a substrate, a bottom electrode layer over and in electrical coupling with the conductive feature, an insulator layer over the bottom electrode layer, a semiconductor layer over the insulator layer, a ferroelectric layer over the semiconductor layer, and a top electrode layer over the ferroelectric layer. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device comprising a chimney seed structure. A ferroelectric layer overlies a bottom electrode layer, and a top electrode layer overlies the ferroelectric layer. The top electrode layer, the ferroelectric layer, and the bottom electrode layer form a plurality of memory cells, and a dielectric wall extends through the top electrode layer and segments the top electrode layer into a plurality top electrodes individual to the memory cells. The chimney seed structure underlies the ferroelectric layer and extends through the bottom electrode layer from the ferroelectric layer. The chimney seed structure is configured to seed ferroelectric crystalline growth in the ferroelectric layer to allow the ferroelectric layer to achieve a large remanent polarization with a small thickness. The small thickness increases read speeds, while the large remanent polarization increases a read window and hence reliability.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A cable management system for a server rack, including an adapter bracket coupled to the server rack; a rail assembly coupled to the adapter bracket, the rail assembly including a plurality of apertures; a cable management apparatus slideably coupled to the rail assembly, the cable management apparatus including: a plunger; a plurality of tabs; and a plurality of retention devices, wherein, when the cable management apparatus is coupled to the rail assembly, the plunger extends through one of the apertures to define a position of the cable management apparatus with respect to the rail assembly such that one or more cables of the server rack are positioned between opposing tabs of the plurality of tabs and coupled to the cable management apparatus by one or more of the retention devices.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing an aluminum nitride layer on the gate dielectric, depositing an aluminum oxide layer on the aluminum nitride layer, performing an annealing process to drive aluminum in the aluminum nitride layer into the gate dielectric, removing the aluminum oxide layer and the aluminum nitride layer, and forming a gate electrode on the gate dielectric.

Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

Abstract: A method for evaluating data to be used to train an object recognition model is to be implemented by a computing device. The computing device stores a plurality of training datasets respectively related to a plurality of images, and each training dataset includes a plurality of entries of training data. The method includes steps of: obtaining, for each image, at least one target area and at least one target property that are related to the image based on the entries of training data; creating, for each image, a training material that includes the image, and the at least one target area and the at least one target property both related to the image; and obtaining at least three object recognition models based on the training materials that are created respectively for the images using at least one machine learning algorithm.

Abstract: A server rack includes a power distribution unit, a first side panel and a second side panel. The power distribution unit is affixed to an outward side of the server rack at a rearward end of the server rack. The first side panel is located at the rearward end of the server rack and covers the first PDU. The first side panel has a first width. The second side panel has a second width, A sum of the first width and the second width is substantially equal to a depth of the server rack.

Abstract: A server information handling system rack has an adjustable depth to fit different sized server rack sleds and adapt the rack to different sized data centers. Fixed vertical supports couple to fixed horizontal supports to define a rack interior that adjusts in depth by sliding horizontal supports that change a position of extensible vertical supports coupled to the sliding horizontal supports. When a desired rack depth is set, the fixed horizontal supports and sliding horizontal supports are affixed to each other, such as with a screw that couples to a threaded nut of the fixed horizontal support.

Abstract: A cable management system for a server rack, including an adapter bracket coupled to the server rack; a rail assembly coupled to the adapter bracket, the rail assembly including a plurality of apertures; a cable management apparatus slideably coupled to the rail assembly, the cable management apparatus including: a plunger; a plurality of tabs; and a plurality of retention devices, wherein, when the cable management apparatus is coupled to the rail assembly, the plunger extends through one of the apertures to define a position of the cable management apparatus with respect to the rail assembly such that one or more cables of the server rack are positioned between opposing tabs of the plurality of tabs and coupled to the cable management apparatus by one or more of the retention devices.