Abstract: An interfacial layer is formed in a manner that enables a ferroelectric layer to be formed such that formation of ferroelectric crystalline phases (e.g., orthorhombic crystalline phases) in the ferroelectric layer is increased and formation of non-ferroelectric crystalline phases (e.g., monoclinic phases, tetragonal phases) in the ferroelectric layer is reduced. To achieve this, the grain size and/or other properties of the interfacial layer may be controlled during formation of the interfacial layer such that the grain size and/or other properties of the interfacial layer facilitate formation of a larger grain size in the ferroelectric layer. At larger grain sizes in the ferroelectric layer, the concentration of the ferroelectric crystalline phases in the crystal structure of the ferroelectric layer may be increased relative to if the ferroelectric layer were formed to a smaller grain size.

Abstract: A test strip detecting system includes a test strip, a test strip detecting carrier and a mobile communication apparatus. The test strip detecting carrier includes a container structure, positioning markers and colorimetric calibrating blocks, and the colorimetric calibrating blocks are embedded inside the positioning markers. The test strip is placed in the container structure and reacts with a specimen to generate color blocks. The mobile communication apparatus controls an image capture unit to capture an original image of the test strip placed in the test strip detecting carrier; detects the positioning markers in the original image to obtain a plurality of coordinates of the positioning markers; performs image coordinate calibration according to the plurality of coordinates to generate a calibrated image; and performs a colorimetric calibration for the color blocks and the colorimetric calibrating blocks according to the calibrated image so as to generate a test result.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: A server information handling system rack has an adjustable depth to fit different sized server rack sleds and adapt the rack to different sized data centers. Fixed vertical supports couple to fixed horizontal supports to define a rack interior that adjusts in depth by sliding horizontal supports that change a position of extensible vertical supports coupled to the sliding horizontal supports. When a desired rack depth is set, the fixed horizontal supports and sliding horizontal supports are affixed to each other, such as with a screw that couples to a threaded nut of the fixed horizontal support.

Abstract: A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

Abstract: A semiconductor device includes a ferroelectric tunnel junction (FTJ), wherein the ferroelectric tunnel junction includes a first electrode, a ferroelectric layer disposed over the first electrode, and a second electrode disposed over the ferroelectric layer. The first electrode contains nitrogen or oxygen and is characterized by a first percentage of nitrogen or oxygen. The second electrode contains nitrogen or oxygen and is characterized by a second percentage of nitrogen or oxygen. The first percentage is different from the second percentage.

Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.

Abstract: A method according to the present disclosure includes forming a plurality of transistors in a first wafer and forming a memory array in a second wafer. A first surface of the first wafer includes a first plurality of bonding pads electrically coupled to the transistors. The memory array includes a plurality of ferroelectric tunnel junction (FTJ) stacks. A second surface of the second wafer includes a second plurality of bonding pads electrically coupled to the FTJ stacks. The method also includes performing a thermal treatment to the FTJ stacks in the second wafer, and after the performing of the thermal treatment, bonding the first surface of the first wafer with the second surface of the second wafer. The transistors are coupled to the memory cells through the first plurality of bonding pads and the second plurality of bonding pads.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: A method for providing drug recommendation includes: calculating a plurality of relative cell viabilities respectively corresponding to a plurality of candidate drugs based on viable cell counts of a patient's circulating tumor cell (CTC)-derived organoid cultures and viable cell counts of the CTC-derived organoid cultures respectively reacted with the candidate drugs; and providing drug recommendation of the candidate drugs based on the relative cell viabilities. A device for providing drug recommendation is also provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect wires and vias arranged within one or more interconnect dielectric layers over a substrate. Further, a bottom electrode is disposed over the one or more interconnect wires and vias and comprises a first material having a first work function. A top electrode is disposed over the bottom electrode and comprises a second material having a second work function. The first material is different than the second material, and the first work function is different than the second work function. An anti-ferroelectric layer is disposed between the top and bottom electrodes.

Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Abstract: A graphical indicator is provided. The graphical indicator includes a plurality of header blocks and a plurality content blocks. The header blocks include N first header blocks and (M?1) second header blocks. Each of the content blocks has a data micro-graphic. The N first header blocks are disposed at a first row of an indicator matrix. Each of the (M?1) second header blocks is disposed at (M?1) rows other than the first row of the indicator matrix. Each of the N first header blocks has a header micro-graphic. Furthermore, one or more target second header blocks in the (M?1) second header blocks do not have the header micro-graphic, and each of a plurality of remaining second header blocks other than the one or more target second header blocks in the (M?1) second header blocks has the header micro-graphic.

Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.

Abstract: A graphical indicator is provided. The graphical indicator includes a plurality of header blocks and a plurality content blocks. The header blocks include N first header blocks and (M?1) second header blocks. Each of the content blocks has a data micro-graphic. The N first header blocks are disposed at a first row of an indicator matrix. Each of the (M?1) second header blocks is disposed at (M?1) rows other than the first row of the indicator matrix. Each of the N first header blocks has a header micro-graphic. Furthermore, one or more target second header blocks in the (M?1) second header blocks do not have the header micro-graphic, and each of a plurality of remaining second header blocks other than the one or more target second header blocks in the (M?1) second header blocks has the header micro-graphic.

Abstract: A stand device includes a base, a supporting component and a carrying component. The supporting component is pivotally disposed to the base along a first axis. The carrying component is pivotally disposed to the supporting component along a second axis, and slidably disposed to the supporting component in a first direction. The stand device is switchable between a first state and a second state. In the first state, the extending direction of the supporting component is parallel to the extending direction of the base, and the extending direction of the carrying component is parallel to the extending direction of the supporting component. In the second state, the extending direction of the supporting component is staggered to the extending direction of the base, and the extending direction of the carrying component is staggered to the extending direction of the supporting component.

Abstract: An LED package structure includes a substrate, an electrode layer and an insulating layer in a coplanar arrangement and disposed on the substrate, an LED chip mounted on the electrode layer and the insulating layer, a phosphor sheet covering entirely a top surface of the LED chip, a first translucent layer disposed on a light emitting surface of the phosphor sheet, and a reflective housing covering the side surfaces of the LED chip and the side surfaces of the phosphor sheet. The light emitting surface has a central region and a ring-shaped region surrounding the central region. The first translucent layer covers at least 60% of an area of the ring-shaped region. A refractive index of the first translucent layer is larger than one and is smaller than that of the phosphor sheet. A top surface of the reflective housing is substantially flush with the light emitting surface.

Abstract: A stand device includes a base, a supporting component and a carrying component. The supporting component is pivotally disposed to the base along a first axis. The carrying component is pivotally disposed to the supporting component along a second axis, and slidably disposed to the supporting component in a first direction. The stand device is switchable between a first state and a second state. In the first state, the extending direction of the supporting component is parallel to the extending direction of the base, and the extending direction of the carrying component is parallel to the extending direction of the supporting component. In the second state, the extending direction of the supporting component is staggered to the extending direction of the base, and the extending direction of the carrying component is staggered to the extending direction of the supporting component.